Register Description
Bits
Type
Reset
Description
15
ROS
0
PCI Address Low (PAL): For PCI-X requests and all PCI cycles, this bit
represents the parity detected in the 1st phase (lower 32-bits) of a dual
address cycle, or just the address of a regular address cycle. For PCI-X
completions, this bit represents the 1st clock (requester attributes) driven in the
completion cycle. When the Intel® 6700PXH 64-bit PCI Hub is driving, this bit
contains the value driven. When the Intel® 6700PXH 64-bit PCI Hub is
receiving, this bit contains the value captured. This is only valid in PCI-X Mode
1 operation.
This bit is logged along with the Secondary Header Log register
(SEC_HDLOG, offset 13Ch) when there is an address parity error (this bit is
never loaded independently of the PCI-X Header Log register). This bit is not
loaded for any other error conditions. This bit remains set until software clears
the corresponding status bit in the Secondary Uncorrectable Error Status
register (SEC_UNC_ERRSTS, offset 12Ch).
14
RWCS
ROS
0
0
REQ# Log Valid (RLV): This bit is set when REQ# log bits (bits 13:11 of this
register) are valid. Clearing this bit will re-enable logging into the REQ# log
register bits.
13:11
REQ# Log (RL): These bits capture the REQ# of the PCI agent mastering the
transaction when the Intel® 6700PXH 64-bit PCI Hub detected a correctable
or uncorrectable address, attribute or data parity error. That is, the REQ# log is
valid when either of the three error conditions occur that cause either of bits
9:7 to be set or any errors occur that cause the error phase register bits in the
Bridge ECC Control and Status register (BG_ECCSTS, offset E8h) to be non-
zero. Once a log is made in the REQ# log, further logging of the REQ# log bits
is stopped till the REQ# log valid bit (bit 14 of this register) is cleared. Note that
this register is not dependent on the clearing of status bits in the Secondary
Uncorrectable Error Status register (SEC_UNC_ERRSTS, offset 12Ch) or the
Bridge ECC Attribute register (BG_ECCATTR, offset F4h), to rearm itself.
000 = REQ0 001 = REQ1
010 = REQ2 011 = REQ3
100 = REQ4: 101 = REQ5
110 = REQ6 111 = Reserved
10
9
RO
0
0
Reserved.
RWCS
Log Valid (LOGV): This is set by the Intel® 6700PXH 64-bit PCI Hub
whenever it logs a value in the Data Log register (offset 14Ch) and also the
byte enable log bits in this register (offset 154h, bits 7:0). Software clears this
register by writing a 1, which will rearm the Data Log register (offset 14Ch) and
enable the byte enable log register bits (bits 7:0 of this register) to start loading
again.
8
ROS
ROS
0
0
Data Bus Width (DBW): This bit is set if the data logged in the Data Log
register is 64 bits. Otherwise this bit is clear. When clear the upper 32 bits of
the Data Log registers are invalid.
7:0
PCI-X Byte Enable Log (PXBEL): This error is logged whenever the Intel®
6700PXH 64-bit PCI Hub is the target of a data transfer and it detects a data
parity/ECC error (correctable or uncorrectable). This register is logged along
with the Data Log register. This register is not defined if the log valid bit (bit 9
above) is not set. This register re-arms itself for loading again when software
clears the log valid bit by writing a one to that bit.
124
Intel® 6700PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
