Register Description
3.6.1.12
Offset 138h: UNC_PXERRPTR – Uncorrectable
PCI/PCI-X Error Pointer Register (D0:F0, F2)
Offset:
Default Value: 00000000h
138 – 13Bh
Attribute: ROS, RO
Size: 32 bits
This register points to the bit position of the first error reported in the Uncorrectable PCI/PCI-X
Error Status register (offset 12Ch). This register is rearmed when the bit position pointed to is
cleared in the associated status register. The pointer value is not updated when this register is
rearmed.
Bits
Type
Reset
Description
31:5
4:0
RO
0
0
Reserved.
ROS
Uncorrectable PCI/PCI-X First Error Pointer (UPFEP): This register points
to the first error that was logged in the Uncorrectable PCI/PCI-X Error Status
register (offset 12Ch). This register rearms itself when the status bit
corresponding to the error which this register is pointing to is cleared by
software writing a 1 to the bit.
3.6.1.13
Offset 13Ch: PX_TXNHDLOG – PCI/PCI-X
Uncorrectable Transaction Header Log (D0:F0, F2)
Offset:
Default Value: 0h
13C – 143h
Attribute: ROS
Size: 128 bits
The log in this register captures the header for the transaction that generated an error. Once an error
is logged in this register, this register is locked from further error loggings, until software clears the status bit
corresponding to the first uncorrectable error that occurred. When this bit is cleared by software, this register
is rearmed for further header logs.
Bits
Type
Reset Description
127:64
ROS
0
Transaction Address (TXNAD): These bits capture the 64-bit value
transferred on PxAD[31:0] during the 1st and 2nd address phase of the
transaction in which an error was detected. The 1st address phase is logged to
bits 95:64 and the 2nd address phase is logged to bits 127:96. In case of a
32-bit address, bits 127:96 will be set to all zeros. The address is logged on all
error conditions.
63:44
43:40
RO
0
0
Reserved.
ROS
Transaction Command Upper (TXNCU): This captures the value of
PxC/BE[3:0]# during the 2nd address phase of a DAC transaction Contains
the 4-bit value transferred on PxC/BE[3:0]# during the 2nd attribute phase of
the transaction.
39:36
35:0
ROS
ROS
0
0
Transaction Command Lower (TXNCL): This captures the value of
PxC/BE[3:0]# during the 1st address phase of the transaction. Contains the
4-bit value transferred on PxC/BE[3:0]# during the 1st attribute phase of the
transaction.
Transaction Attribute (TXNAT): This carries the attribute of the transaction.
Contains the 36-bit value transferred on PxC/BE[3:0]# and PxAD[31:0]) during
the attribute phase of the transaction.
When the bus is in PCI mode, these bits are all zeros.
122
Intel® 6700PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
