Register Description
3.6.1.14
Offset 14Ch: PX_DERRLOG – PCI-X Uncorrectable
Data Error Log Register (D0:F0, F2)
Offset:
14C – 153h
Attribute: ROS
Size: 64 bits
Default Value: 0000000000000000h
This register is logged for all correctable or uncorrectable data parity errors.
Bits
Type
Reset
Description
63:0
ROS
0
PCI-X Data Log (PDL): This register is logged with the PCI data bus value
whenever the Intel® 6700PXH 64-bit PCI Hub is the target of a data transfer
and it detects a data parity error (correctable or uncorrectable). This register is
not defined if the log valid bit in the error log and control register is not set. This
register re-arms itself for loading again when software clears the log valid bit by
writing a 1 to that bit. For 32-bit data transfers, only the lower 32 bits are
logged.
3.6.1.15
Offset 154h: PX_MISCERRLOG – Other PCI-X
Error Logs and Control Register (D0:F0, F2)
Offset:
154 – 155h
Attribute: RWCS, ROS, RO
Size: 32 bits
Default Value: 0000000000000000h
This register contains bits logged for uncorrectable data parity errors (in PCI or PCI-X Mode 1),
uncorrectable address/attribute parity errors and PCI REQ# line of failure.
Bits
Type
Reset
Description
31:19
18
RO
0
0
Reserved.
ROS
Data Log (DATA_LOG): A “1” indicates the data log is from a correctable ECC
data error. A 0 indicates the data log is from an uncorrectable ECC/parity error.
This bit is logged along with the DLOG register and is rearmed when the log
valid bit is cleared. This is also only valid when the log valid bit is set by the
Intel® 6700PXH 64-bit PCI Hub.
17
ROS
0
PCI-X Attribute Parity (PP): This bit indicates that parity was detected in the
attribute phase of a request and completion. When the Intel® 6700PXH 64-bit
PCI Hub is driving, it is the value driven. When the Intel® 6700PXH 64-bit PCI
Hub is receiving, it is the value captured. This bit is only valid in PCI-X Mode 1
operation.
This bit is logged along with the Secondary Header Log register
(SEC_HDLOG, offset 13Ch) when there is an attribute parity error. This bit is
not loaded for any other error conditions. This bit remains set until software
clears the corresponding status bit in the Secondary Uncorrectable Error
Status register (SEC_UNC_ERRSTS, offset 12Ch).
16
ROS
0
PCI Address High (PAH): This bit represents the parity detected in the 2nd
phase (upper 32-bits) of a dual address cycle. This bit is forced to ‘0’ if the
address was a single address cycle. When the Intel® 6700PXH 64-bit PCI
Hub is driving, this bit contains the value driven. When the Intel® 6700PXH
64-bit PCI Hub is receiving, this bit contains the value captured. This is only
valid in PCI-X Mode 1 operation.
This bit is logged along with the Secondary Header Log register
(SEC_HDLOG, offset 13Ch) when there is an address parity error (this bit is
never loaded independently of the Secondary Header Log register). This bit is
not loaded for any other error conditions. This bit remains set until software
clears the corresponding status bit in the Secondary Uncorrectable Error
Status register (SEC_UNC_ERRSTS, offset 12Ch).
Intel® 6700PXH 64-bit PCI Hub Datasheet
123
INTEL [ INTEL ]
