Register Description
Bits
Type
Reset
Description
5:1
0
RO
0
0
Reserved.
RWS
Receiver Error Mask (REM): The Intel® 6700PXH 64-bit PCI Hub sets this bit
when the physical layer detects a receiver error.
3.6.1.7
Offset 118h: ADVERR_CNTL – Advanced Error
Capabilities and Control Register (D0:F0, F2)
Offset:
Default Value: 00000000h
118 – 11Bh
Attribute: ROS, RO
Size: 32 bits
The register gives the status and control for ECRC checks and also the pointer to the first
uncorrectable error that happened.
Bits
Type
Reset
Description
31:9
8
RO
RO
0
0
Reserved.
ECRC Check Enable (ECR): The Intel® 6700PXH 64-bit PCI Hub does not
support ECRC check and this bit is reserved.
7
6
RO
RO
0
0
ECRC Check Capable (ECCAP): The Intel® 6700PXH 64-bit PCI Hub is not
ECRC check capable.
ECRC Generation Enable (EGE): The Intel® 6700PXH 64-bit PCI Hub cannot
generate an ECRC and this bit is ignored by the Intel® 6700PXH 64-bit PCI
Hub.
5
RO
0
0
ECRC Generation Capable (EGC): The Intel® 6700PXH 64-bit PCI Hub
cannot generate an ECRC.
4:0
ROS
First Error Pointer (FEPTR): Identifies the bit position of the first error
reported in the Uncorrectable Error Status register. This register re-arms itself
(but does not change in value) once the error status bit pointed to by the
pointer is cleared by software by writing a 1 to that status bit.
3.6.1.8
Offset 11Ch: EXP_TXNHDLOG – PCI Express*
Transaction Header Log Register (D0:F0, F2)
Offset:
Default Value: 0
11C – 11Fh
Attribute: ROS
Size: 128 bits
This is a transaction header log for PCI Express* errors. Captures the header for the TLP
corresponding to a detected error. Refer to Section 6.2 of the PCI Express* Base Specification,
Revision 1.0a for details.
Bits
Type
Reset
Description
127:0
ROS
0
Header of the TLP associated with the error. Once an error is logged in this
register, it remains locked for further error loggings until such time software
clears the status bit, which re-enables logging of the next error event.
118
Intel® 6700PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
