Register Description
Bits
Type
Reset
Description
13
12
11:5
4
RWS
RWS
RO
0
0
0
0
0
0
Flow Control Protocol Error Mask (FCPEM)
Poisoned TLP Mask (PTLPM)
Reserved.
RWS
RO
Data Link Protocol Error Mask (DLPEM)
Reserved.
3:1
0
RO
Training Error Mask (TEM): Not applicable to the Intel® 6700PXH 64-bit PCI
Hub.
3.6.1.4
Offset 10Ch: ERRUNC_SEV – PCI Express*
Uncorrectable Error Severity Register (D0:F0, F2)
Offset:
Default Value: 00030010h
10C – 10Fh
Attribute: RWS, RO
Size: 32 bits
This register controls whether an individual uncorrectable error is reported as a fatal or non-fatal
error. An uncorrectable error is reported as fatal (ERR_FATAL) when the corresponding error bit in
this register is set to 1. If the bit is cleared, the corresponding error is considered non-fatal
(ERR_NONFATAL). Refer to Section 6.2 of the PCI Express* Base Specification, Revision 1.0a
for details.
Bits
Type
Reset
Description
31:21
20
RO
RWS
RO
0
0
0
Reserved.
Unsupported Request Error Severity (URES)
19
ECRC Error Severity (EES): Not applicable to the Intel® 6700PXH 64-bit PCI
Hub.
18
17
16
15
14
13
12
11:5
4
RWS
RWS
RWS
RWS
RWS
RWS
RWS
RO
1
1
0
0
0
0
0
0
1
0
0
Malformed TLP Severity (MTLPS)
Receiver Overflow Error Severity (ROFES)
Unexpected Completion Error Severity (UCES)
Completer Abort Error Mask (CAEM)
Completion Timeout Error Severity (CTES)
Flow Control Protocol Error Severity (FCPES)
Poisoned TLP Received (PTLPR)
Reserved.
RWS
RO
Data Link Protocol Error Severity (DLPES)
Reserved.
3:1
0
RO
Training Error Severity (TES): Not applicable to the Intel® 6700PXH 64-bit
PCI Hub.
116
Intel® 6700PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
