Register Description
Bits
Type
Reset
Description
16
RWCS
0
Unexpected Completion Status (EC_STS): The Intel® 6700PXH 64-bit PCI
Hub sets this bit whenever it receives a completion with a requestor ID that
does not match either bus segment A or B, or when it receives a completion
with a matching requestor ID but an unexpected tag field. The Intel® 6700PXH
64-bit PCI Hub logs the header of the unexpected completion.
15
14
RWCS
RWCS
0
0
Completer Abort Status (CA_STS): The Intel® 6700PXH 64-bit PCI Hub sets
this bit and logs the header associated with the request when the SHPC
signals a completer abort. The Intel® 6700PXH 64-bit PCI Hub logs the
header.
Completion Timeout Status (CT_STS): The Intel® 6700PXH 64-bit PCI Hub
sets this bit when inbound memory, configuration, or I/O reads do not receive
completions within 16-32ms.
13
12
RWCS
RWCS
0
0
Flow Control Protocol Error Status (FCP_STS): The Intel® 6700PXH 64-bit
PCI Hub sets this bit when there is a flow control protocol error detected.
Poisoned TLP Status (PTLP_STS): The Intel® 6700PXH 64-bit PCI Hub sets
this bit when a poisoned TLP is received from PCI Express*. The Intel®
6700PXH 64-bit PCI Hub logs the header of the poisoned TLP packet.
11:5
4
RO
0
0
Reserved.
RWCS
Data Link Protocol Error Status (DLP_STS): The Intel® 6700PXH 64-bit PCI
Hub sets this bit when there is a data link protocol error detected.
3:1
0
RO
RO
0
0
Reserved.
Training Error (TE): The Intel® 6700PXH 64-bit PCI Hub does not set this bit.
3.6.1.3
Offset 108h: ERRUNC_MSK – PCI Express*
Uncorrectable Error Mask Register (D0:F0, F2)
Offset:
Default Value: 00000000h
108 – 10Bh
Attribute: RWS, RO
Size: 32 bits
This register controls reporting of individual uncorrectable errors by the Intel® 6700PXH 64-bit
PCI Hub to the host bridge via a PCI Express* error message and also the logging of the header.
Refer to the PCI Express* Base Specification Revision 1.0a for details of how the mask bits
function. A masked error, a respective bit set to 1 in the mask register, is not reported to the host
bridge by the Intel® 6700PXH 64-bit PCI Hub, and is not logged in the Header Log register (offset
11Ch - status bits unaffected by the mask bit) and does not update the First Error Pointer (FEPTR,
offset 118h, bit 4). There is a mask bit per error bit of the Uncorrectable Error Status register (offset
104h). Refer to Section 6.2 of the PCI Express* Base Specification, Revision 1.0a for details.
Bits
Type
Reset
Description
31:21
20
RO
RWS
RO
0
0
0
Reserved.
Unsupported Request Error Mask (UREM)
19
ECRC Error Mask (EEM): Not applicable to the Intel® 6700PXH 64-bit PCI
Hub.
18
17
16
15
14
RWS
RWS
RWS
RWS
RWS
0
0
0
0
0
Malformed TLP Mask (MTLPM)
Receiver Overflow Mask (ROFM)
Unexpected Completion Mask (UCM)
Completer Abort Mask (CAM)
Completion Timeout Mask (CTM)
Intel® 6700PXH 64-bit PCI Hub Datasheet
115
INTEL [ INTEL ]
