Register Description
3.6
PCI Express* to PCI Bridges (D0:F0, F2) Enhanced
The enhanced PCI Express* configuration access mechanism utilizes a flat memory-mapped
address space to access device configuration registers. In this case, the memory address determines
the configuration register accessed and the memory data returns the contents of the addressed
register. Refer to the Section 7.9 in the PCI Express* Base Specification, Revision 1.0a for details.
3.6.1
Configuration Registers
3.6.1.1
Offset 100h: ENH_CAP – PCI Express* Enhanced
Capability Register (D0:F0, F2)
Offset:
Default Value: 30010001h
100 – 103h
Attribute: RO
Size: 32 bits
All PCI Express* extended capabilities must begin with a PCI Express* Enhanced Capabilities
Register.
Bits
Type
Reset
Description
31:20
RO
300h
Next Capability Offset (NCO): Contains the offset to the next PCI Express*
Capability Structure, which in this case is power budgeting capability.
19:16
15:0
RO
RO
1h
1h
Capability Version (CAP_VER): PCI-SIG defined PCI Express* Advanced
Error Reporting Extended Capability Version Number.
PCI Express* Extended Capability ID (EXP_XCAPID): PCI-SIG defined PCI
Express* Extended Capability ID indicating Advanced Error Reporting
Capability.
3.6.1.2
Offset 104h: ERRUNC_STS – PCI Express*
Uncorrectable Error Status Register (D0:F0, F2)
Offset:
Default Value: 00000000h
104 – 107h
Attribute: RWCS, RO
Size: 32 bits
This register reports error status of individual uncorrectable error sources. An individual error
status bit that is set to “1” indicates that a particular error occurred; software may clear an error
status by writing a 1 to the respective bit. Refer to Section 6.2 of the PCI Express* Base
Specification, Revision 1.0a for details.
Bits
Type
Reset
Description
31:21
20
RO
0
0
Reserved.
RWCS
Unsupported Request Error Status (URE_STS): Set by the Intel® 6700PXH
64-bit PCI Hub whenever an unsupported request is detected on the PCI
Express* interface including those signaled by the SHPC (on write data parity
errors – configuration and memory).
19
18
17
RWCS
RWCS
RWCS
0
0
0
ECRC Error Status (ECRC_STS): The Intel® 6700PXH 64-bit PCI Hub does
not do ECRC check and this bit is never set.
Malformed TLP Status (MTLP_STS): The Intel® 6700PXH 64-bit PCI Hub
sets this bit when it receives a malformed TLP. Header logging is done.
Receiver Overflow Status (RO_STS): The Intel® 6700PXH 64-bit PCI Hub
would set this if the PCI Express* interface received buffers overflow.
114
Intel® 6700PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
