Register Description
3.5.1.59
3.5.1.60
3.5.1.61
Offset ECh: PX_ECCFA – Bridge ECC Error First Address
Register (D0:F0, F2)
Offset:
Default Value: 00000000h
EC – EFh
Attribute: ROS
Size: 32 bits
Least significant address bits of the failing transaction.
Bits
Type
Reset
Description
31:0
ROS
0
ECC First Address (ECC_FA): If the ECC Error Phase register is non-zero
(indicating that an error has been captured), this register indicates the
contents of the AD[31::00] bus for the address phase of the transaction that
included the error. If the ECC Error Phase is zero, the contents of this register
are undefined. This register always records the least significant 32 bits of the
address, regardless of the type or length of the transaction, or the phase in
which the error occurred. The Intel® 6700PXH 64-bit PCI Hub stores
information from the failing transaction directly from the bus (uncorrected),
even if correction of the error is possible.
Offset F0h: PX_ECCSA – Bridge ECC Error Second
Address Register (D0:F0, F2)
Offset:
Default Value: 00000000h
F0 – F3h
Attribute: ROS
Size: 32 bits
Most significant address bits of the failing transaction.
Bits
Type
Reset Description
ECC Second Address (ECC_SA): If the ECC Error Phase register is non-zero
31:0
ROS
0
(indicating that an error has been captured), this register indicates the contents
of the AD[63::32] bus for the address phase of the transaction that included the
error. If the ECC Error Phase is zero, the contents of this register are
undefined. This register always records the most significant 32 bits of the
address, regardless of the type or length of the transaction, or the phase in
which the error occurred. The Intel® 6700PXH 64-bit PCI Hub stores
information from the failing transaction directly from the bus (uncorrected),
even if correction of the error is possible.
Offset F4h: BG_ECCATTR — Bridge ECC Attribute
Register (D0:F0, F2)
Offset:
Default Value: 00000000h
F4 – F7h
Attribute: ROS
Size: 32 bits
Describes the attributes of the ECC.
Bits
Type
Reset
Description
31:0
ROS
0
ECC Attribute (ECC_AT): If the ECC Error Phase register bits are non-zero
(indicating that an error has been captured), the ECC Attribute register
indicates the contents of the AD[31::00] bus for the attribute phase of the
transaction that included the error. If the ECC Error Phase registers is zero,
the contents of this register are undefined. This register records the contents
of the bus during the attribute phase, regardless of the type or length of the
transaction, or the phase in which the error occurred. The Intel® 6700PXH
64-bit PCI Hub stores information in this register from the failing transaction
directly from the bus (uncorrected), even if correction of the error is possible.
Intel® 6700PXH 64-bit PCI Hub Datasheet
113
INTEL [ INTEL ]
