Register Description
3.5.1.58
Offset DCh: PX_BSTS—PCI-X Bridge Status Register
(D0:F0, F2)
Offset:
DC – DFh
Attribute: RWC, RO
Size: 32 bits
Default Value: 00030000h (PCI Bus A)
00030002h (PCI Bus B, Intel® 6700PXH 64-bit PCI Hub only)
Bits
Type
Reset
Description
31
30
29
RO
RO
RO
0
0
0
Reserved.
Reserved.
Device ID Messaging Capable (DIDMC): The Intel® 6700PXH 64-bit PCI
Hub is not capable of forwarding DIM transactions. Hardwired to 0.
28:22
21
RO
0
0
Reserved.
RWC
Split Request Delayed (SRD): Hardwired to 0. This bit is not supported
by the Intel® 6700PXH 64-bit PCI Hub, because it will never be in a
position where it cannot issue a request.
20
19
RO
RO
0
0
Split Completion Overrun (SCO): Hardwired to 0. This bit is not set by
the Intel® 6700PXH 64-bit PCI Hub because the Intel® 6700PXH 64-bit
PCI Hub never requests on the PCI Express* interface more data than it
has room to receive.
Unexpected Split Completion (USC): The Intel® 6700PXH 64-bit PCI
Hub sets this field when a completion on the PCI Express* bus is destined
to one of the PCI bus segment (either A or B) but the tag does not match.
18
17
RO
RO
RO
RO
RO
RO
0
1
1
0
0
Split Completion Discarded (SCD): Hardwired to 0. This does not apply
to the PCI Express* interface.
133 MHz Capable (C133): Hardwired to 1. This field does not apply to PCI
Express*.
16
64-bit Device (D64): This field really does not apply to the PCI Express*
interface, but is set to '1' to be software-compatible.
15:8
7:3
2:0
Bus Number (BNUM): This field is an alias to the PBN field of the BNUM
register at offset 18h.
Device Number (DNUM): The device number is 0 for both Intel®
6700PXH 64-bit PCI Hub bridge segments.
Bus A – 0h Function Number (FNUM):
Bus B – 2h
0h for PCI segment A.
2h for PCI segment B (Intel® 6700PXH 64-bit PCI Hub).
112
Intel® 6700PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
