Register Description
3.5.1.56
Offset D9h: PX_NXTCP—PCI-X Next Capabilities Pointer
Register (D0:F0, F2)
Offset:
Default Value: 00h
D9h
Attribute: RO
Size: 8 bits
This register points to the next item in the Capabilities List, as required by the PCI 2.3
Specification.
Bits
Type
Reset
Description
7:0
RO
0h
Next Capabilities Pointer (NCPTR): This is the last capability structure for
Intel® 6700PXH 64-bit PCI Hub, so it is hardwired to 0.
3.5.1.57
Offset DAh: PX_SSTS—PCI-X Secondary Status
Register (D0:F0, F2)
Offset:
Default Value: 0003h
DA–DBh
Attribute: RWC, RO
Size: 16 bits
This register controls various modes and features of the PCI-X device.
Bits
Type
Reset
Description
15:9
8:6
RO
RO
0
x
Reserved.
Secondary Clock Frequency (SCF): This field is set with the frequency of
the secondary bus. The values are:
Bits Max Frequency
Clock Period
000
001
010
011
1xx
PCI Mode
N/A
15
66 PCI-X Mode 1
100 PCI-X Mode 1
133 PCI-X Mode 1
Reserved
10
7.5
5
4
3
RO
RO
0
0
0
Split Request Delayed. (SRD): The Intel® 6700PXH 64-bit PCI Hub will
never set this bit.
Split Completion Overrun (SCO): The Intel® 6700PXH 64-bit PCI Hub will
never set this bit.
RWC
Unexpected Split Completion (USC):
0 = This bit is cleared by writing a 1 to it.
1 = This bit is set if an unexpected split completion with a requester ID equal
to the Intel® 6700PXH 64-bit PCI Hub PCI/PCI-X secondary bus number is
received on the PCI/PCI-X interface.
2
RWC
0
Split Completion Discarded (SCD):
0 = This bit is cleared by writing a 1 to it.
1 = Intel® 6700PXH 64-bit PCI Hub discarded a split completion moving
toward the secondary bus because the requester would not accept it.
1
0
RO
RO
1
1
133 MHz Capable (C133): Hardwired to 1; indicates that the Intel® 6700PXH
64-bit PCI Hub’s PCI/PCI-X interface is capable of 133 MHz operation in
PCI-X mode.
64-bit Device (D64): Hardwired to 1; indicates the width of the PCI/PCI-X bus
is 64 bits.
Intel® 6700PXH 64-bit PCI Hub Datasheet
111
INTEL [ INTEL ]
