Registers
Device:
NodeID
Function: 6
Offset:
C0h
Bit
Attr
Default
Description
2
RWCST
0
COMPLETE: IBIST done flag
0: Not done
1: Done
1
0
RWST
RWST
0
0
MSTRMD: Master Mode Enable
When this bit is set along with IBISTR, the Intel IBIST transmit engine is
enabled to transmit Intel IBIST patterns.
0: Disable Master mode.
1: Enable master mode.
IBISTR: IBIST Start
When set, Intel IBIST starts transmitting after the TS1 header is recognized
during the next link initialization sequence. and MSTRMD bit is set.This bit also
enables the receive engine to start looking for the start delimiter during TS1
training set. This bit is reset when Intel IBIST receiver is done. The Intel IBIST
transmit and receive engines can be stopped by setting this bit to 0.
0: Stop IBIST transmitter
1: Start IBIST transmitter
14.8.3.2
NBFIBPGCTL: NB Intel IBIST Pattern Generator Control Register
This register contains bits to control the operation of the Intel IBIST pattern generator.
All counts are in 24 bit increments.
Device:
NodeID
Function: 6
Offset:
Bit
C4h
Attr
Default
Description
OVRLOOPCNT: Overall Loop Count
31:26 RWST
0Fh
0h: Reserved
1h-3Fh: Number of times to loop all the patterns.
25:21 RWST
00h
CNSTGENCNT: Constant Generator Loop Counter
00h: Disable constant generator output
01h: 1Fh The number of times the constant generator counter pattern should loop
before going to the next component. Each count represents 24 bits of 1’s or 0’s.
20
RWST
0
CNSTGENSET: Constant Generator Setting
0: Generate 0
1: Generate 1
19:13 RWST
12:10 RWST
0Fh
MODLOOPCNT: Modulo-N Loop Counter
Each count represents 24 bits of the pattern specified by MODPERIOD.
00h: Disable Pattern Output
01h: 7Fh The number of times the Pattern Buffer should loop before going to the
next component.
001b
MODPERIOD: Period of the Modulo-N counter
Each encoding transmits a 24-bit pattern as specified below. All other encodings are
reserved.
001: L/2 - 0101_0101_0101_0101_0101_0101
010: L/4 - 0011_0011_0011_0011_0011_0011
011: L/6 - 0001_1100_0111_0001_1100_0111
100: L/8 - 0000_1111_0000_1111_0000_1111
110: L/24 - 0000_0000_0000_1111_1111_1111
9:3
RWST
0Fh
PATTLOOPCNT: Pattern Buffer Loop Counter
00h: Disable Pattern Output
01h: 7Fh The number of times the Pattern Buffer (IBPATTBUF) should be repeated
before going to the next component.
Intel® 6400/6402 Advanced Memory Buffer Datasheet
237
INTEL [ INTEL ]
