Registers
14.8.2.5
SBFIBRXMSK: SB Intel IBIST Receiver Mask Register
This register enables Intel IBIST operations for individual lanes. This mask only applies
to receivers and not transmitters.
Device:
NodeID
Function: 6
Offset:
Bit
90h
Attr
Default
Description
31:10
9:0
RV
000000h
3FFh
Reserved
RXMASK: Selects which channels to enable for testing.
RWST
14.8.2.6
SBFIBTXSHFT: SB Intel IBIST Transmitter Inversion Shift Register
Each bit in this register enables inverting the patterns that is driven on corresponding
lanes. If AUTOINVSWPEN bit is set in port control register, the TXINVSHFT field is
rotated left at the completion of each pattern buffer set.
Device:
NodeID
Function: 6
Offset:
Bit
94h
Attr
Default
Description
31:10
9:0
RV
000000h
3FFh
Reserved
TXINVSHFT: Transmitter Inversion Shift Register.
RWST
14.8.2.7
SBFIBRXSHFT: SB Intel IBIST Receiver Inversion Shift Register
Each bit in this register enables inverting the patterns that is received on corresponding
lanes. If AUTOINVSWPEN bit is set in port control register, the RXINVSHFT field is
rotated left at the completion of each pattern buffer set.
Device:
NodeID
Function: 6
Offset:
Bit
98h
Attr
Default
Description
31:10
9:0
RV
000000h
3FFh
Reserved
RXINVSHFT: Receiver Inversion Shift Register.
RWST
14.8.2.8
SBFIBRXLNERR: SB Intel IBIST Receiver Lane Error Status
This records the error status from each lane.
Device:
NodeID
Function: 6
Offset:
Bit
9Ch
Attr
Default
Description
31:10
9:0
RV
000000h
000h
Reserved
RXERRSTAT: Receiver Error Status
ROST
234
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL ]
