Registers
14.8.3.6
NBFIBTXSHFT: NB Intel IBIST Transmitter Inversion Shift Register
Each bit in this register enables inverting the patterns that is driven on corresponding
lanes. If AUTOINVSWPEN bit is set in port control register, the TXINVSHFT field is
rotated left at the completion of each pattern buffer set.
Device:
NodeID
Function: 6
Offset:
Bit
D4h
Attr
Default
Description
31:14
13:0
RV
00000h
3FFFh
Reserved
TXINVSHFT: Transmitter Inversion Shift Register.
RWST
14.8.3.7
NBFIBRXSHFT: NB Intel IBIST Receiver Inversion Shift Register
Each bit in this register enables inverting the patterns that is received on corresponding
lanes. If AUTOINVSWPEN bit is set in port control register, the RXINVSHFT field is
rotated left at the completion of each pattern buffer set.
Device:
NodeID
Function: 6
Offset:
Bit
D8h
Attr
Default
Description
31:14
13:0
RV
00000h
3FFFh
Reserved
RXINVSHFT: Receiver Inversion Shift Register.
RWST
14.8.3.8
NBFIBRXLNERR: NB Intel IBIST Receiver Lane Error Status
This records the error status from each lane.
Device:
NodeID
Function: 6
Offset:
Bit
DCh
Attr
Default
Description
31:14
13:0
RV
00000h
0000h
Reserved
RXERRSTAT: Receiver Error Status
ROST
14.8.3.9
NBFIBPATTBUF2: NB Intel IBIST Pattern Buffer 2 Register
This optional register contains the pattern bits used in Intel IBIST operations. Only the
least significant 24 bits are used. This user specified pattern goes out on to the link
with the least-significant 12 bits as the first frame and the most significant 12 bits as
the second frame.
Device:
NodeID
Function: 6
Offset:
Bit
E0h
Attr
Default
Description
31:24
23:0
RV
00h
Reserved
RWST
fd3302h
IBPATBUF2: IBIST Pattern Buffer 2
Pattern buffer storing the default and the user programmable pattern.
Intel® 6400/6402 Advanced Memory Buffer Datasheet
239
INTEL [ INTEL ]
