Registers
Device:
NodeID
Function: 6
Offset:
Bit
84h
Attr
Default
Description
12:10 RWST
001b
MODPERIOD: Period of the Modulo-N counter
Each encoding transmits a 24-bit pattern as specified below. All other encodings are
reserved.
001: L/2 - 0101_0101_0101_0101_0101_0101
010: L/4 - 0011_0011_0011_0011_0011_0011
011: L/6 - 0001_1100_0111_0001_1100_0111
100: L/8 - 0000_1111_0000_1111_0000_1111
110: L/24 - 0000_0000_0000_1111_1111_1111
9:3
2:0
RWST
RWST
0Fh
000
PATTLOOPCNT: Pattern Buffer Loop Counter
00h: Disable Pattern Output
01h: 7Fh The number of times the Pattern Buffer (FIBPATTBUF1) should be
repeated before going to the next component.
PTGENORD: Pattern Generation Order
000: Pattern Store + Modulo N Cntr + Constant Generator
001: Pattern Store + Constant Generator + Modulo N Cntr
010: Modulo N Cntr + Pattern Store + Constant Generator
011: Modulo N Cntr + Constant Generator + Pattern Store
100: Constant Generator + Pattern Store + Modulo N Cntr
101: Constant Generator + Modulo N Cntr + Pattern Store
110: Reserved
111: Reserved
14.8.2.3
SBFIBPATTBUF1: SB Intel IBIST Pattern Buffer 1 Register
This register contains the pattern bits used in Intel IBIST operations. Only the least
significant 24 bits are used. This user specified pattern goes out on to the link with the
least-significant 12 bits as the first frame and the most significant 12 bits as the
second frame.
Device:
NodeID
Function: 6
Offset:
Bit
88h
Attr
Default
Description
31:24
23:0
RV
RWST
00h
02ccfdh
Reserved
IBPATBUF: IBIST Pattern Buffer
Pattern buffer storing the default and the user programmable
pattern.
Default: 02ccfdh
14.8.2.4
SBFIBTXMSK: SB Intel IBIST Transmitter Mask Register
This register enables Intel IBIST operations for individual lanes. This mask only applies
to transmitters and not receivers.
Device:
NodeID
Function: 6
Offset:
Bit
8Ch
Attr
Default
Description
31:10
9:0
RV
000000h
3FFh
Reserved
TXMASK: Selects which channels to enable for testing.
RWST
Intel® 6400/6402 Advanced Memory Buffer Datasheet
233
INTEL [ INTEL ]
