欢迎访问ic37.com |
会员登录 免费注册
发布采购

6400 参数 Datasheet PDF下载

6400图片预览
型号: 6400
PDF下载: 下载PDF文件 查看货源
内容描述: 高级内存缓冲器 [Advanced Memory Buffer]
分类和应用:
文件页数/大小: 250 页 / 3863 K
品牌: INTEL [ INTEL ]
 浏览型号6400的Datasheet PDF文件第232页浏览型号6400的Datasheet PDF文件第233页浏览型号6400的Datasheet PDF文件第234页浏览型号6400的Datasheet PDF文件第235页浏览型号6400的Datasheet PDF文件第237页浏览型号6400的Datasheet PDF文件第238页浏览型号6400的Datasheet PDF文件第239页浏览型号6400的Datasheet PDF文件第240页  
Registers  
14.8.2.12 SBIBISTMISC: SB Intel IBIST Initialization Miscellaneous Register  
This register control southbound Intel IBIST Testing.  
Device:  
NodeID  
Function: 6  
Offset:  
Bit  
B4h  
Attr  
Default  
00h  
Description  
31:  
RV  
Reserved  
23:20  
19:0  
RWST  
RWST  
0h  
AMBID: Value of the AMB ID field during TS0  
61a80h  
SBIBISTCALPERIOD: Number of cycles to drive 1 during  
Calibration  
14.8.3  
Northbound FBD Intel IBIST Registers  
14.8.3.1  
NBFIBPORTCTL: Northbound FBD Intel IBIST Port Control Register  
This register controls the operation of the Intel IBIST logic.  
Device:  
NodeID  
Function: 6  
Offset:  
Bit  
C0h  
Attr  
Default  
Description  
31:24  
23  
RV  
00h  
0
Reserved  
RWST  
SBNBMAP: Loopback mapping bit  
This bit will be sent during TS1 to specify to the slave which lanes needs to be  
looped back. Actual lanes looped back is specified in the FBD Architecture Spec.  
22  
RWST  
0
CMMSTR: Compliance Measurement Mode start  
This puts the Intel IBIST logic in CMM mode and Intel IBIST TX engine will start  
transmitting Intel IBIST patterns.  
21:12  
11:8  
RWCST  
ROST  
000h  
0h  
ERRCNT: Error Counter  
Total number of frames with errors that were encountered by this port.  
ERRLNNUM: Error Lane Number  
This points to the first lane that encountered an error. If more than one lane  
reports an error in a cycle, the most significant lane number that reported the  
error will be logged.  
7:6  
RWCST  
00  
ERRSTAT: Port Error Status  
When Intel IBIST is started, status goes to 01 until first start delimiter is  
received and then goes to 00 until the end or to10 if an error occurs.  
00: No error.  
01: Did not receive first start delimiter.  
10: Transmission error (first error).  
11: Reserved  
5
RWST  
0
AUTOINVSWPEN: Auto Inversion sweep enable  
This bit enables the inversion shift register to continuously rotate the pattern in  
the FIBTXSHFT and FIBRXSHFT registers.  
0: Disable Auto-inversion  
1: Enable Auto-inversions  
4
3
RWST  
RWST  
0
0
STOPONERR: Stop IBIST on Error  
0: Do not stop on error, only update error counter  
1: Stop on error  
LOOPCON: Loop forever  
0: No looping  
1: Loop forever  
236  
Intel® 6400/6402 Advanced Memory Buffer Datasheet  
 复制成功!