Registers
14.8.2.9
SBFIBPATTBUF2: SB Intel IBIST Pattern Buffer 2 Register
This optional register contains the pattern bits used in Intel IBIST operations. Only the
least significant 24 bits are used. This user specified pattern goes out on to the link
with the least-significant 12 bits as the first frame and the most significant 12 bits as
the second frame.
Device:
NodeID
Function: 6
Offset:
Bit
A0h
Attr
Default
Description
31:24
23:0
RV
00h
Reserved
RWST
fd3302h
IBPATBUF2: IBIST Pattern Buffer 2
Pattern buffer storing the default and the user programmable pattern.
Default: fd3302h
14.8.2.10 SBFIBPATT2EN: SB Intel IBIST Pattern Buffer 2 Enable
This optional register specifies which lanes will carry the pattern specified in
SBFIBPATTBUFF2.
Device:
NodeID
Function: 6
Offset:
Bit
A4h
Attr
Default
Description
31:10
9:0
RV
00h
Reserved
RWST
000h
SBFIBPATT2EN: IBIST Pattern Buffer 2 enable
Per lane enable for driving pattern buffer 2.
14.8.2.11 SBFIBINIT: SB Intel IBIST Initialization Register
This register control southbound Intel IBIST Testing.
Device:
NodeID
Function: 6
Offset:
Bit
B0h
Attr
Default
Description
31
RV
0
Reserved
30:21
RWST
0c8h
SBTS0CNT: Southbound TS0 Count
Number of TS0 sequences to transmit.
20:13
RWST
01h
SBTS1CNT: Southbound TS1 Count
Number of TS1 sequences to transmit.
If TS1CNT[7] = 1; (TS1CNT >= 128) Intel IBIST will loop forever
If TS1CNT[7] = 0; (TS1CNT <128) Intel IBIST will loop TS1CNT
times
12:3
2
RWST
RWST
100h
1
SBDISCNT: Southbound Disable State Count
Number of cycles to remain in disable state.
SBCALIBEN: Southbound Calibration Enable
1 - Perform FBD Calibration.
1
0
RV
0
0
Reserved
RWST
SBIBISTINITEN: IBIST Initialization Enable
1 - Start IBIST Testing with Southbound Transmitter as the host.
Intel® 6400/6402 Advanced Memory Buffer Datasheet
235
INTEL [ INTEL ]
