Registers
14.8.3.10 NBFIBPATT2EN: NB Intel IBIST Pattern Buffer 2 Enable
This optional register specifies which lanes will carry the pattern specified in
NBFIBPATTBUFF2.
Device:
NodeID
Function: 6
Offset:
Bit
E4h
Attr
Default
Description
15:14
13:0
RV
00
Reserved
RWST
0000h
IBPATBUF2EN: IBIST Pattern Buffer 2 enable
Per lane enable for driving pattern buffer 2.
14.8.3.11 NBFIBINIT: NB Intel IBIST Initialization Register
This register control northbound Intel IBIST Testing.
Device:
NodeID
Function: 6
Offset:
F0h
Bit
Attr
Default
Description
31
RWST
0
SBIDLE: SB Link is not active
This is to enable the NB link to complete training when there is no activity on
the SB side. Normally NB waits for SB init to complete before proceeding with
its training.
0 - Wait for SB
1 - Do not wait for SB
30:21 RWST
20:13 RWST
0c8h
01h
NBTS0CNT: Northbound TS0 Count
Number of TS0 sequences to transmit.
NBTS1CNT: Northbound TS1 Count
Number of TS1 sequences to transmit.
If TS1CNT[7] = 1; (TS1CNT >= 128) Intel IBIST will loop forever
If TS1CNT[7] = 0; (TS1CNT <128) Intel IBIST will loop TS1CNT times
12:3
RWST
RWST
100h
NBDISCNT: Northbound Disable State Count
Number of cycles to remain in disable state.
2
1
1
0
NBCALIBEN: Northbound Calibrating Enable
1 - Perform FBD Calibration.
RV
Reserved
0
RWST
0
NBIBISTINITEN: IBIST Initialization Enable
1 - Start IBIST Testing with Northbound Transmitter as the host.
14.8.3.12 NBIBISTMISC: NB Intel IBIST Initialization Miscellaneous Register
This register control northbound Intel IBIST Testing.
Device:
NodeID
Function: 6
Offset:
F4h
Attr
RV
Bit
Default
00h
Description
31
Reserved
23:20 RWST
19:0 RWST
0h
AMBID: Value of the AMB ID field during TS0
61a80h
NBIBISTCALPERIOD: Number of cycles to drive 1 during Calibration
240
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL ]
