Registers
Device:
NodeID
Function: 6
Offset:
C4h
Bit
Attr
Default
Description
PTGENORD: Pattern Generation Order
2:0
RWST
000
000: Pattern Store + Modulo N Cntr + Constant Generator
001: Pattern Store + Constant Generator + Modulo N Cntr
010: Modulo N Cntr + Pattern Store + Constant Generator
011: Modulo N Cntr + Constant Generator + Pattern Store
100: Constant Generator + Pattern Store + Modulo N Cntr
101: Constant Generator + Modulo N Cntr + Pattern Store
110: Reserved
111: Reserved
14.8.3.3
NBFIBPATTBUF1: NB Intel IBIST Pattern Buffer 1 Register
This register contains the pattern bits used in Intel IBIST operations. Only the least
significant 24 bits are used. This user specified pattern goes out on to the link with the
least-significant 12 bits as the first frame and the most significant 12 bits as the second
frame.
Device:
NodeID
Function: 6
Offset:
Bit
C8h
Attr
Default
Description
31:24
23:0
RV
00h
Reserved
RWST
02ccfdh
IBPATBUF: IBIST Pattern Buffer
Pattern buffer storing the default and the user programmable pattern.
14.8.3.4
NBFIBTXMSK: NB Intel IBIST Transmitter Mask Register
This register enables Intel IBIST operations for individual lanes. This mask only applies
to transmitters and not receivers.
Device:
NodeID
Function: 6
Offset:
Bit
CCh
Attr
Default
Description
31:14
13:0
RV
00000h
3FFFh
Reserved
TXMASK: Selects which channels to enable for testing.
RWST
14.8.3.5
NBFIBRXMSK: NB Intel IBIST Receiver Mask Register
This register enables Intel IBIST operations for individual lanes. This mask only applies
to receivers and not transmitters.
Device:
NodeID
Function: 6
Offset:
Bit
D0h
Attr
Default
Description
31:14
13:0
RV
00000h
3FFFh
Reserved
RXMASK: Selects which channels to enable for testing.
RWST
238
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL ]
