Switching Characteristics
Page 45
Table 36. High-Speed I/O Specifications for Stratix V Devices (1), (2) (Part 2 of 4)
C1
C2, C2L, I2, I2L C3, I3, I3L, I3YY
C4,I4
Symbol
Conditions
Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Transmitter
SERDES factor J
(9), (11),
= 3 to 10
(6)
(6)
(6)
(6)
(6)
(6)
(6)
(6)
—
—
1600
1600
—
—
1434
1600
—
—
1250
1600
—
—
1050 Mbps
1250 Mbps
(12), (13), (14), (15),
(16)
SERDES factor J
4
True
LVDS TX with
(12) (14), (15),
Differential
I/O Standards
- fHSDR (data
rate)
DPA
,
(16)
SERDES factor J
= 2,
(6)
(6)
(7)
(7)
(6)
(6)
(7)
(7)
(6)
(6)
(7)
(7)
(6)
(6)
(7)
—
—
—
—
—
—
—
—
Mbps
uses DDR
Registers
SERDES factor J
= 1,
(7)
Mbps
uses SDR
Register
Emulated
Differential
I/O Standards
with Three
External
SERDES factor J
= 4 to 10
(6)
(6)
(6)
(6)
—
1100
—
1100
—
840
—
840 Mbps
(17)
Output
Resistor
Networks -
fHSDR (data
(10)
rate)
Total Jitter for
Data Rate
600 Mbps -
1.25 Gbps
—
—
—
—
—
—
160
0.1
—
—
—
—
—
—
160
0.1
—
—
—
—
—
—
160
0.1
—
—
—
—
—
—
160
0.1
ps
UI
ps
tx Jitter - True
Differential
I/O Standards
Total Jitter for
Data Rate
< 600 Mbps
tx Jitter
-
Total Jitter for
Data Rate
600 Mbps - 1.25
Gbps
Emulated
Differential
I/O Standards
with Three
External
Output
Resistor
300
300
300
325
Total Jitter for
Data Rate
< 600 Mbps
—
—
0.2
—
—
0.2
—
—
0.2
—
—
0.25
UI
Network
December 2015 Altera Corporation
Stratix V Device Datasheet
INTEL [ INTEL ]
