Switching Characteristics
Page 41
Table 31. PLL Specifications for Stratix V Devices (Part 3 of 3)
Symbol
fRES
Parameter
Min
Typ
Max
Unit
Hz
Resolution of VCO frequency (fINPFD = 100 MHz)
390625
5.96
0.023
Notes to Table 31:
(1) This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
standard.
(2) This specification is limited by the lower of the two: I/O fMAX or fOUT of the PLL.
(3) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source < 120 ps.
(4) fREF is fIN/N when N = 1.
(5) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies
to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a
different measurement method and are available in Table 44 on page 52.
(6) The cascaded PLL specification is only applicable with the following condition:
a. Upstream PLL: 0.59Mhz Upstream PLL BW < 1 MHz
b. Downstream PLL: Downstream PLL BW > 2 MHz
(7) High bandwidth PLL settings are not supported in external feedback mode.
(8) The external memory interface clock output jitter specifications use a different measurement method, which is available in Table 42 on page 50.
(9) The VCO frequency reported by the Quartus II software in the PLL Usage Summary section of the compilation report takes into consideration
the VCO post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification.
(10) This specification only covers fractional PLL for low bandwidth. The fVCO for fractional value range 0.05 - 0.95 must be 1000 MHz, while fVCO
for fractional value range 0.20 - 0.80 must be 1200 MHz.
(11) This specification only covered fractional PLL for low bandwidth. The fVCO for fractional value range 0.05-0.95 must be 1000 MHz.
(12) This specification only covered fractional PLL for low bandwidth. The fVCO for fractional value range 0.20-0.80 must be 1200 MHz.
DSP Block Specifications
Table 32 lists the Stratix V DSP block performance specifications.
Table 32. Block Performance Specifications for Stratix V DSP Devices (Part 1 of 2)
Peformance
Mode
Unit
I3, I3L,
I3YY
C1
C2, C2L I2, I2L
C3
C4
I4
Modes using one DSP
Three 9 x 9
One 18 x 18
600
600
600
600
500
500
600
600
600
500
500
480
480
480
480
400
400
420
420
MHz
600
600
500
500
480
480
400
400
420
420
350
350
400
400
350
350
MHz
MHz
MHz
MHz
Two partial 18 x 18 (or 16 x 16)
One 27 x 27
One 36 x 18
One sum of two 18 x 18(One sum of
2 16 x 16)
500
500
500
400
400
350
350
MHz
One sum of square
500
500
500
500
500
500
400
400
400
400
350
350
350
350
MHz
MHz
One 18 x 18 plus 36 (a x b) + c
Modes using two DSPs
Three 18 x 18
500
475
465
475
500
475
500
475
465
475
500
475
500
475
450
475
500
475
400
380
380
380
400
380
400
380
380
380
400
380
350
300
300
300
350
300
350
300
290
300
350
300
MHz
MHz
MHz
MHz
MHz
MHz
One sum of four 18 x 18
One sum of two 27 x 27
One sum of two 36 x 18
One complex 18 x 18
One 36 x 36
December 2015 Altera Corporation
Stratix V Device Datasheet
INTEL [ INTEL ]
