Page 42
Switching Characteristics
Table 32. Block Performance Specifications for Stratix V DSP Devices (Part 2 of 2)
Peformance
Mode
Unit
I4
I3, I3L,
I3YY
C1
C2, C2L I2, I2L
C3
C4
Modes using Three DSPs
425 415 340
Modes using Four DSPs
465 465 380
One complex 18 x 25
One complex 27 x 27
425
340
275
265
290
MHz
MHz
465
380
300
Memory Block Specifications
Table 33 lists the Stratix V memory block specifications.
Table 33. Memory Block Performance Specifications for Stratix V Devices (1), (2) (Part 1 of 2)
Resources Used
ALUTs Memory
Performance
I3,
Memory
Mode
Unit
C2,
C2L
C1
C3
C4
I2, I2L I3L,
I3YY
I4
Single port, all
supported widths
0
0
0
0
1
1
1
1
450
450
675
600
450
450
675
600
400
400
533
500
315
315
400
450
450
450
675
600
400
400
533
500
315 MHz
315 MHz
400 MHz
450 MHz
Simple dual-port,
x32/x64 depth
MLAB
Simple dual-port, x16
depth (3)
ROM, all supported
widths
Stratix V Device Datasheet
December 2015 Altera Corporation
INTEL [ INTEL ]
