Switching Characteristics
Page 49
Table 38. LVDS Soft-CDR/DPA Sinusoidal Jitter Mask Values for a Data Rate 1.25 Gbps
Jitter Frequency (Hz) Sinusoidal Jitter (UI)
F1
F2
F3
F4
10,000
17,565
25.000
25.000
0.350
1,493,000
50,000,000
0.350
Figure 8 shows the LVDS soft-CDR/DPA sinusoidal jitter tolerance specification for a
data rate < 1.25 Gbps.
Figure 8. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for a Data Rate < 1.25 Gbps
Sinusoidal Jitter Amplitude
20db/dec
0.1 UI
P-P
Frequency
20 MHz
baud/1667
DLL Range, DQS Logic Block, and Memory Output Clock Jitter Specifications
Table 39 lists the DLL range specification for Stratix V devices. The DLL is always in
8-tap mode in Stratix V devices.
(1)
Table 39. DLL Range Specifications for Stratix V Devices
C1
300-933
C2, C2L, I2, I2L
C3, I3, I3L, I3YY
C4,I4
Unit
300-933
300-890
300-890
MHz
Note to Table 39:
(1) Stratix V devices support memory interface frequencies lower than 300 MHz, although the reference clock that feeds the DLL must be at least
300 MHz. To support interfaces below 300 MHz, multiply the reference clock feeding the DLL to ensure the frequency is within the supported
range of the DLL.
Table 40 lists the DQS phase offset delay per stage for Stratix V devices.
(1), (2)
Table 40. DQS Phase Offset Delay Per Setting for Stratix V Devices
(Part 1 of 2)
Unit
Speed Grade
C1
Min
8
Max
14
ps
ps
ps
C2, C2L, I2, I2L
C3,I3, I3L, I3YY
8
14
8
15
December 2015 Altera Corporation
Stratix V Device Datasheet
INTEL [ INTEL ]
