Switching Characteristics
Page 47
Table 36. High-Speed I/O Specifications for Stratix V Devices (1), (2) (Part 4 of 4)
C1
C2, C2L, I2, I2L C3, I3, I3L, I3YY
C4,I4
Symbol
Conditions
Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
SERDES factor J
= 3 to 10
(6)
(6)
(8)
(7)
(6)
(6)
(8)
(7)
(6)
(6)
(8)
(7)
(6)
(6)
(8)
(7)
—
—
—
—
—
—
—
—
Mbps
SERDES factor J
= 2,
Mbps
Mbps
fHSDR (data
rate)
uses DDR
Registers
SERDES factor J
= 1,
(6)
(7)
(6)
(7)
(6)
(7)
(6)
(7)
—
—
—
—
uses SDR
Register
DPA Mode
DPA run
length
1000
0
1000
0
1000
0
1000
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UI
Soft CDR mode
Soft-CDR
PPM
tolerance
300
300
300
300
300
300
300
300
PPM
ps
Non DPA Mode
Sampling
Window
Notes to Table 36:
(1) When J = 3 to 10, use the serializer/deserializer (SERDES) block.
(2) When J = 1 or 2, bypass the SERDES block.
(3) This only applies to DPA and soft-CDR modes.
(4) Clock Boost Factor (W) is the ratio between the input data rate to the input clock rate.
(5) This is achieved by using the LVDS clock network.
(6) The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional,
or local) that you use. The I/O differential buffer and input register do not have a minimum toggle rate.
(7) The maximum ideal frequency is the SERDES factor (J) x the PLL maximum output frequency (fOUT) provided you can close the design timing
and the signal integrity simulation is clean.
(8) You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board
skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.
(9) If the receiver with DPA enabled and transmitter are using shared PLLs, the minimum data rate is 150 Mbps.
(10) You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew
margin, transmitter channel-to-channel skew, and receiver sampling margin to determine leftover timing margin.
(11) The FMAX specification is based on the fast clock used for serial data. The interface FMAX is also dependent on the parallel clock domain which
is design-dependent and requires timing analysis.
(12) Stratix V RX LVDS will need DPA. For Stratix V TX LVDS, the receiver side component must have DPA.
(13) Stratix V LVDS serialization and de-serialization factor needs to be x4 and above.
(14) Requires package skew compensation with PCB trace length.
(15) Do not mix single-ended I/O buffer within LVDS I/O bank.
(16) Chip-to-chip communication only with a maximum load of 5 pF.
(17) When using True LVDS RX channels for emulated LVDS TX channel, only serialization factors 1 and 2 are supported.
December 2015 Altera Corporation
Stratix V Device Datasheet
INTEL [ INTEL ]
