Page 48
Switching Characteristics
Figure 6 shows the dynamic phase alignment (DPA) lock time specifications with the
DPA PLL calibration option enabled.
Figure 6. DPA Lock Time Specification with DPA PLL Calibration Enabled
rx_reset
DPA Lock Time
rx_dpa_locked
256 data
transitions
96 slow
clock cycles
256 data
transitions
96 slow
clock cycles
256 data
transitions
Table 37 lists the DPA lock time specifications for Stratix V devices.
Table 37. DPA Lock Time Specifications for Stratix V GX Devices Only (1), (2), (3)
Number of Data
Number of
Transitions in One
Standard
Training Pattern
Repetitions per 256
Maximum
Repetition of the
Training Pattern
(4)
Data Transitions
SPI-4
00000000001111111111
00001111
2
2
4
8
8
128
128
64
640 data transitions
640 data transitions
640 data transitions
640 data transitions
640 data transitions
Parallel Rapid I/O
10010000
10101010
32
Miscellaneous
01010101
32
Notes to Table 37:
(1) The DPA lock time is for one channel.
(2) One data transition is defined as a 0-to-1 or 1-to-0 transition.
(3) The DPA lock time stated in this table applies to both commercial and industrial grade.
(4) This is the number of repetitions for the stated training pattern to achieve the 256 data transitions.
Figure 7 shows the LVDS soft-clock data recovery (CDR)/DPA sinusoidal jitter
tolerance specification for a data rate 1.25 Gbps. Table 38 lists the LVDS
soft-CDR/DPA sinusoidal jitter tolerance specification for a data rate 1.25 Gbps.
Figure 7. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for a Data Rate 1.25 Gbps
LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification
25
8.5
0.35
0.1
F3
F2
F1
F4
Jitter Frequency (Hz)
Stratix V Device Datasheet
December 2015 Altera Corporation
INTEL [ INTEL ]
