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Switching Characteristics
Periphery Performance
This section describes periphery performance, including high-speed I/O and external
memory interface.
I/O performance supports several system interfaces, such as the LVDS high-speed
I/O interface, external memory interface, and the PCI/PCI-X bus interface.
General-purpose I/O standards such as 3.3-, 2.5-, 1.8-, and 1.5-LVTTL/LVCMOS are
capable of a typical 167 MHz and 1.2-LVCMOS at 100 MHz interfacing frequency
with a 10 pF load.
1
The actual achievable frequency depends on design- and system-specific factors.
Ensure proper timing closure in your design and perform HSPICE/IBIS simulations
based on your specific design and system setup to determine the maximum
achievable frequency in your system.
High-Speed I/O Specification
Table 36 lists high-speed I/O timing for Stratix V devices.
Table 36. High-Speed I/O Specifications for Stratix V Devices (1), (2) (Part 1 of 4)
C1
C2, C2L, I2, I2L C3, I3, I3L, I3YY
C4,I4
Symbol
Conditions
Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
fHSCLK_in(input
clock
frequency)
True
Clock boost factor
W = 1 to 40
5
5
—
—
800
800
5
5
—
—
800
800
5
5
—
—
625
5
5
—
—
525
MHz
(4)
Differential
I/O Standards
fHSCLK_in(input
clock
frequency)
Single Ended
I/O
Clock boost factor
W = 1 to 40
625
420
525
420
MHz
(4)
Standards (3)
fHSCLK_in(input
clock
frequency)
Single Ended
I/O Standards
Clock boost factor
5
5
—
—
520
800
5
5
—
—
520
800
5
5
—
—
5
5
—
—
MHz
MHz
(4)
W = 1 to 40
fHSCLK_OUT
(output clock
frequency)
625
525
—
(5)
(5)
Stratix V Device Datasheet
December 2015 Altera Corporation
INTEL [ INTEL ]
