Page 46
Switching Characteristics
Table 36. High-Speed I/O Specifications for Stratix V Devices (1), (2) (Part 3 of 4)
C1
C2, C2L, I2, I2L C3, I3, I3L, I3YY
C4,I4
Unit
Symbol
Conditions
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Transmitter
output clock duty
cycle for both
True and
tDUTY
45 50
55
45 50
55
45 50
55
45 50
55
%
Emulated
Differential I/O
Standards
True Differential
I/O Standards
—
—
—
—
160
250
—
—
—
—
160
250
—
—
—
—
200
250
—
—
—
—
200
300
ps
ps
Emulated
Differential I/O
Standards with
three external
output resistor
networks
tRISE & tFALL
True Differential
I/O Standards
—
—
—
—
150
300
—
—
—
—
150
300
—
—
—
—
150
300
—
—
—
—
150
300
ps
ps
TCCS
Emulated
Differential I/O
Standards
Receiver
SERDES factor J
(11), (12),
= 3 to 10
150
150
—
—
1434 150
1600 150
—
—
1434 150
1600 150
—
—
1250 150
1600 150
—
—
1050 Mbps
1250 Mbps
(13), (14), (15), (16)
SERDES factor J
4
LVDS RX with
True
(12), (14), (15),
DPA
Differential
I/O Standards
- fHSDRDPA
(data rate)
(16)
SERDES factor J
= 2,
(6)
(6)
(7)
(7)
(6)
(6)
(7)
(7)
(6)
(6)
(7)
(7)
(6)
(6)
(7)
—
—
—
—
—
—
—
—
Mbps
uses DDR
Registers
SERDES factor J
= 1,
(7)
Mbps
uses SDR
Register
Stratix V Device Datasheet
December 2015 Altera Corporation
INTEL [ INTEL ]
