Page 40
Switching Characteristics
Table 31. PLL Specifications for Stratix V Devices (Part 2 of 3)
Symbol
Parameter
Min
—
Typ
—
Max
0.15
+750
Unit
Input clock cycle-to-cycle jitter (fREF ≥ 100 MHz)
Input clock cycle-to-cycle jitter (fREF < 100 MHz)
UI (p-p)
ps (p-p)
(3), (4)
tINCCJ
–750
—
Period Jitter for dedicated clock output (fOUT
100 MHz)
≥
(1)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
175
ps (p-p)
mUI (p-p)
ps (p-p)
mUI (p-p)
ps (p-p)
mUI (p-p)
ps (p-p)
mUI (p-p)
ps (p-p)
mUI (p-p)
ps (p-p)
mUI (p-p)
ps (p-p)
mUI (p-p)
ps (p-p)
mUI (p-p)
ps (p-p)
mUI (p-p)
%
(5)
tOUTPJ_DC
Period Jitter for dedicated clock output (fOUT
100 MHz)
<
(1)
17.5
Period Jitter for dedicated clock output in fractional
PLL (fOUT 100 MHz)
250 (11)
175 (12)
,
(5)
tFOUTPJ_DC
tOUTCCJ_DC
tFOUTCCJ_DC
Period Jitter for dedicated clock output in fractional
PLL (fOUT < 100 MHz)
25 (11)
,
17.5 (12)
Cycle-to-Cycle Jitter for a dedicated clock output
(fOUT ≥ 100 MHz)
175
(5)
(5)
Cycle-to-Cycle Jitter for a dedicated clock output
(fOUT < 100 MHz)
17.5
Cycle-to-cycle Jitter for a dedicated clock output in
fractional PLL (fOUT 100 MHz)
250 (11)
175 (12)
,
Cycle-to-cycle Jitter for a dedicated clock output in
fractional PLL (fOUT < 100 MHz)+
25 (11)
,
17.5 (12)
Period Jitter for a clock output on a regular I/O in
integer PLL (fOUT ≥ 100 MHz)
600
(5),
tOUTPJ_IO
(8)
Period Jitter for a clock output on a regular I/O
(fOUT < 100 MHz)
60
600 (10)
60 (10)
600
Period Jitter for a clock output on a regular I/O in
fractional PLL (fOUT 100 MHz)
(5),
tFOUTPJ_IO
(8) (11)
,
Period Jitter for a clock output on a regular I/O in
fractional PLL (fOUT < 100 MHz)
Cycle-to-cycle Jitter for a clock output on a regular I/O
in integer PLL (fOUT 100 MHz)
(5),
(5),
tOUTCCJ_IO
(8)
Cycle-to-cycle Jitter for a clock output on a regular I/O
in integer PLL (fOUT < 100 MHz)
60 (10)
600 (10)
60
Cycle-to-cycle Jitter for a clock output on a regular I/O
in fractional PLL (fOUT 100 MHz)
tFOUTCCJ_IO
(8) (11)
,
Cycle-to-cycle Jitter for a clock output on a regular I/O
in fractional PLL (fOUT < 100 MHz)
Period Jitter for a dedicated clock output in cascaded
PLLs (fOUT ≥ 100 MHz)
175
tCASC_OUTPJ_DC
(5), (6)
Period Jitter for a dedicated clock output in cascaded
PLLs (fOUT < 100 MHz)
17.5
Frequency drift after PFDENA is disabled for a duration
of 100 µs
fDRIFT
—
24
10
32
dKBIT
Bit number of Delta Sigma Modulator (DSM)
Numerator of Fraction
8
Bits
—
kVALUE
128
8388608 2147483648
Stratix V Device Datasheet
December 2015 Altera Corporation
INTEL [ INTEL ]
