Switching Characteristics
Page 39
PLL Specifications
Table 31 lists the Stratix V PLL specifications when operating in both the commercial
junction temperature range (0° to 85°C) and the industrial junction temperature range
(–40° to 100°C).
Table 31. PLL Specifications for Stratix V Devices (Part 1 of 3)
Symbol
Parameter
Min
Typ
Max
Unit
Input clock frequency (C1, C2, C2L, I2, and I2L speed
grades)
5
—
800 (1)
MHz
fIN
Input clock frequency (C3, I3, I3L, and I3YY speed
grades)
5
—
800 (1)
MHz
Input clock frequency (C4, I4 speed grades)
Input frequency to the PFD
5
5
—
—
—
650 (1)
325
MHz
MHz
MHz
fINPFD
fFINPFD
Fractional Input clock frequency to the PFD
50
160
PLL VCO operating range (C1, C2, C2L, I2, I2L speed
grades)
600
600
—
—
1600
1600
MHz
MHz
(9)
fVCO
PLL VCO operating range (C3, I3, I3L, I3YY speed
grades)
PLL VCO operating range (C4, I4 speed grades)
600
40
—
—
1300
60
MHz
%
tEINDUTY
Input clock or external feedback clock input duty cycle
Output frequency for an internal global or regional
clock (C1, C2, C2L, I2, I2L speed grades)
—
—
—
—
—
—
—
—
—
—
—
—
717 (2)
MHz
MHz
MHz
MHz
MHz
MHz
Output frequency for an internal global or regional
clock (C3, I3, I3L speed grades)
(2)
fOUT
650
Output frequency for an internal global or regional
clock (C4, I4 speed grades)
580 (2)
800 (2)
Output frequency for an external clock output (C1, C2,
C2L, I2, I2L speed grades)
Output frequency for an external clock output (C3, I3,
I3L speed grades)
(2)
fOUT_EXT
667
Output frequency for an external clock output (C4, I4
speed grades)
(2)
553
Duty cycle for a dedicated external clock output (when
set to 50%)
tOUTDUTY
tFCOMP
45
—
—
50
—
—
55
10
%
ns
External feedback clock compensation time
Dynamic Configuration Clock used for mgmt_clkand
scanclk
fDYCONFIGCLK
100
MHz
Time required to lock from the end-of-device
configuration or deassertion of areset
tLOCK
—
—
—
—
1
1
ms
ms
Time required to lock dynamically (after switchover or
reconfiguring any non-post-scale counters/delays)
tDLOCK
PLL closed-loop low bandwidth
—
—
—
—
10
0.3
1.5
4
—
—
—
50
—
MHz
MHz
MHz
ps
fCLBW
PLL closed-loop medium bandwidth
(7)
PLL closed-loop high bandwidth
tPLL_PSERR
tARESET
Accuracy of PLL phase shift
—
—
Minimum pulse width on the aresetsignal
ns
December 2015 Altera Corporation
Stratix V Device Datasheet
INTEL [ INTEL ]
