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Switching Characteristics
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XFI
ASI
HiGig/HiGig+
HiGig2/HiGig2+
Serial Data Converter (SDC)
GPON
SDI
SONET
Fibre Channel (FC)
PCIe
QPI
SFF-8431
Download the Stratix V Characterization Report Tool to view the characterization
report summary for these protocols.
Core Performance Specifications
This section describes the clock tree, phase-locked loop (PLL), digital signal
processing (DSP), memory blocks, configuration, and JTAG specifications.
Clock Tree Specifications
Table 30 lists the clock tree specifications for Stratix V devices.
(1)
Table 30. Clock Tree Performance for Stratix V Devices
Performance
Symbol
Unit
C1, C2, C2L, I2, and
I2L
C3, I3, I3L, and
I3YY
C4, I4
Global and
Regional Clock
717
550
650
500
580
500
MHz
MHz
Periphery Clock
Note to Table 30:
(1) The Stratix V ES devices are limited to 600 MHz core clock tree performance.
Stratix V Device Datasheet
December 2015 Altera Corporation
INTEL [ INTEL ]
