Page 40
Switching Characteristics
Figure 9 shows the timing diagram for RGMII TX timing characteristics.
Figure 9. RGMII TX Timing Diagram
TX_CLK
TX_D[3:0]
Td
TX_CTL
Table 43 lists the RGMII RX timing characteristics for Cyclone V devices.
Table 43. RGMII RX Timing Requirements for Cyclone V Devices
Symbol Description
Min
—
—
—
1
Typ
8
Unit
ns
T
clk (1000Base-T)
Tclk (100Base-T)
Tclk (10Base-T)
Tsu
RX_CLK clock period
RX_CLK clock period
RX_CLK clock period
40
400
—
—
ns
ns
RX_D/RX_CTL setup time
RX_D/RX_CTL hold time
ns
Th
1
ns
Figure 10 shows the timing diagram for RGMII RX timing characteristics.
Figure 10. RGMII RX Timing Diagram
RX_CLK
Th
Tsu
RX_D[3:0]
RX_CTL
Table 44 lists the management data input/output (MDIO) timing characteristics for
Cyclone V devices.
Table 44. MDIO Timing Requirements for Cyclone V Devices
Symbol Description
Min
—
10
10
0
Typ
400
—
Unit
ns
Tclk
Td
Ts
MDC clock period
MDC to MDIO output data delay
Setup time for MDIO data
Hold time for MDIO data
ns
—
ns
Th
—
ns
Cyclone V Device Datasheet
July 2014 Altera Corporation
INTEL [ INTEL ]
