Switching Characteristics
Page 39
Figure 7 shows the timing diagram for SD/MMC timing characteristics.
Figure 7. SD/MMC Timing Diagram
SDMMC_CLK_OUT
Td
SDMMC_CMD & SDMMC_D (Out)
SDMMC_CMD & SDMMC_D (In)
Command/Data Out
Tdinmax
Command/Data In
USB Timing Characteristics
Table 41 lists the USB timing characteristics for Cyclone V devices.
Table 41. USB Timing Requirements for Cyclone V Devices
Symbol Description
USB CLK clock period
Min
—
4.4
2
Typ
16.67
—
Max
—
Unit
Tclk
Td
ns
ns
ns
ns
CLK to USB_STP/USB_DATA[7:0] output delay
Setup time for USB_DIR/USB_NXT/USB_DATA[7:0]
Hold time for USB_DIR/USB_NXT/USB_DATA[7:0]
11
Tsu
Th
—
—
1
—
—
Figure 8 shows the timing diagram for USB timing characteristics.
Figure 8. USB Timing Diagram
USB_CLK
USB_STP
Td
USB_DATA[7:0]
To PHY
From PHY
Tsu Th
USB_DIR & USB_NXT
Ethernet Media Access Controller (EMAC) Timing Characteristics
Table 42 lists the reduced gigabit media independent interface (RGMII) TX timing
characteristics for Cyclone V devices.
Table 42. RGMII TX Timing Requirements for Cyclone V Devices
Symbol Description
clk (1000Base-T) TX_CLK clock period
Tclk (100Base-T) TX_CLK clock period
Min
—
Typ
8
Max
—
Unit
ns
T
—
40
400
—
—
—
ns
Tclk (10Base-T)
Tdutycycle
Td
TX_CLK clock period
—
—
ns
TX_CLK duty cycle
45
55
%
TX_CLK to TXD/TX_CTL output data delay
–0.85
0.15
ns
July 2014 Altera Corporation
Cyclone V Device Datasheet
INTEL [ INTEL ]
