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Switching Characteristics
Figure 15 shows the timing diagram for NAND data write timing characteristics.
Figure 15. NAND Data Write Timing Diagram
NAND_CLE
NAND_CE
Tcleh
Tceh
Twp
NAND_WE
Talesu
NAND_ALE
Tdsu
Tdh
NAND_DQ[7:0]
Din
Figure 16 shows the timing diagram for NAND data read timing characteristics.
Figure 16. NAND Data Read Timing Diagram
Tcea
NAND_CE
Trr
Trp
Treh
NAND_RE
Trhz
NAND_RB
Trea
NAND_DQ[7:0]
Dout
ARM Trace Timing Characteristics
Table 47 lists the ARM trace timing characteristics for Cyclone V devices.
Most debugging tools have a mechanism to adjust the capture point of trace data.
Table 47. ARM Trace Timing Requirements for Cyclone V Devices
Description
Min
12.5
45
Max
—
55
1
Unit
ns
CLK clock period
CLK maximum duty cycle
%
CLK to D0 –D7 output data delay
–1
ns
Cyclone V Device Datasheet
July 2014 Altera Corporation
INTEL [ INTEL ]
