Switching Characteristics
Page 37
SPI Timing Characteristics
Table 38 lists the serial peripheral interface (SPI) master timing characteristics for
Cyclone V devices. The setup and hold times can be used for Texas Instruments SSP
mode and National Semiconductor Microwire mode.
Table 38. SPI Master Timing Requirements for Cyclone V Devices
Symbol Description
Min
—
45
8
Max
16.67
55
Unit
ns
Tclk
CLK clock period
Tdutycycle
Tdssfrst
Tdsslst
Tdio
SPI_CLK duty cycle
%
Output delay SPI_SS valid before first clock edge
Output delay SPI_SS valid after last clock edge
Master-out slave-in (MOSI) output delay
—
ns
8
—
ns
–1
1
ns
Maximum data input delay from falling edge of SPI_CLK to
data arrival at SoC. The RX sample delay register can be
programmed to control the capture of input data.
Tdinmax
—
—
—
500
ns
ns
Slave select pulse width (Texas Instruments SSP mode)
16.67
Figure 5 shows the timing diagram for SPI master timing characteristics.
Figure 5. SPI Master Timing Diagram
Tdsslst
SPI_SS
Tdssfrst
SPI_CLK (scpol = 0)
SPI_CLK (scpol = 1)
Tdio
SPI_MOSI (scph = 1)
SPI_MISO (scph = 1)
Tdinmax
Tdio
SPI_MOSI (scph = 0)
SPI_MISO (scph = 0)
Tdinmax
Table 39 lists the SPI slave timing characteristics for Cyclone V devices. The setup and
hold times can be used for Texas Instruments SSP mode and National Semiconductor
Microwire mode.
Table 39. SPI Slave Timing Requirements for Cyclone V Devices
Symbol Description
Min
20
5
Max
—
Unit
ns
Tclk
Ts
CLK clock period
MOSI Setup time
MOSI Hold time
—
ns
Th
5
—
ns
July 2014 Altera Corporation
Cyclone V Device Datasheet
INTEL [ INTEL ]
