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Switching Characteristics
NAND Timing Characteristics
Table 46 lists the NAND timing characteristics for Cyclone V devices.
The NAND controller supports Open NAND FLASH Interface (ONFI) 1.0 Mode 5
timing as well as legacy NAND devices. The following table lists the requirements for
ONFI 1.0 mode 5 timing. The HPS NAND controller can meet this timing by
programming the C4 output of the main HPS PLL and timing registers provided in the
NAND controller.
Table 46. NAND ONFI 1.0 Timing Requirements for Cyclone V Devices
Symbol
(1)
Description
Write enable pulse width
Min
10
7
Max
—
—
—
—
—
—
—
—
—
—
—
—
25
16
100
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Twp
Twh
(1)
Write enable hold time
(1)
Trp
Read Enable pulse width
10
7
(1)
(1)
Treh
Read enable hold time
Tclesu
Command latch enable to write enable setup time
Command latch enable to write enable hold time
Chip enable to write enable setup time
Chip enable to write enable hold time
Address latch enable to write enable setup time
Address latch enable to write enable hold time
Data to write enable setup time
10
5
(1)
Tcleh
(1)
Tcesu
15
5
(1)
Tceh
(1)
Talesu
10
5
(1)
Taleh
(1)
Tdsu
10
5
(1)
Tdh
Tcea
Trea
Trhz
Trr
Data to write enable hold time
Chip enable to data access time
—
—
—
20
Read enable to data access time
Read enable to data high impedance
Ready to read enable low
Note to Table 46:
(1) Timing of the NAND interface is controlled through the NAND Configuration registers.
Cyclone V Device Datasheet
July 2014 Altera Corporation
INTEL [ INTEL ]
