Page 38
Switching Characteristics
Table 39. SPI Slave Timing Requirements for Cyclone V Devices
Symbol
Tsuss
Description
Min
8
Max
—
—
6
Unit
ns
Setup time SPI_SS valid before first clock edge
Hold time SPI_SS valid after last clock edge
Master-in slave-out (MISO) output delay
Thss
Td
8
ns
—
20
ns
—
Slave select pulse width (Texas Instruments SSP mode)
—
ns
Figure 6 shows the timing diagram for SPI slave timing characteristics.
Figure 6. SPI Slave Timing Diagram
Thss
SPI_SS
Tsuss
SPI_CLK (scpol = 0)
SPI_CLK (scpol = 1)
SPI_MISO (scph = 1)
SPI_MOSI (scph = 1)
Td
Ts
Th
Td
SPI_MISO (scph = 0)
SPI_MOSI (scph = 0)
Ts
Th
SD/MMC Timing Characteristics
Table 40 lists the secure digital (SD)/MultiMediaCard (MMC) timing characteristics
for Cyclone V devices.
Table 40. SD/MMC Timing Requirements for Cyclone V Devices
Symbol
Description
Min
20
Max
—
—
55
6
Unit
ns
SDMMC_CLK_OUT clock period (High speed mode)
SDMMC_CLK_OUT clock period (Default speed mode)
SDMMC_CLK_OUT duty cycle
Tclk
40
ns
Tdutycycle
Td
45
%
SDMMC_CMD/SDMMC_D output delay
—
ns
Maximum input delay from rising edge of SDMMC_CLK to
data arrival at SoC
Tdinmax
—
25
ns
Cyclone V Device Datasheet
July 2014 Altera Corporation
INTEL [ INTEL ]
