Switching Characteristics
Page 43
Figure 13 shows the timing diagram for NAND command latch timing characteristics.
Figure 13. NAND Command Latch Timing Diagram
NAND_CLE
NAND_CE
Tclesu
Tcesu
Tcleh
Twp
Tceh
NAND_WE
NAND_ALE
Talesu
Taleh
Tdsu
Command
Tdh
NAND_DQ[7:0]
Figure 14 shows the timing diagram for NAND address latch timing characteristics.
Figure 14. NAND Address Latch Timing Diagram
NAND_CLE
NAND_CE
Tcesu
Tclesu
Twp
Twh
NAND_WE
NAND_ALE
Talesu
Taleh
Tdsu
Tdh
NAND_DQ[7:0]
Address
July 2014 Altera Corporation
Cyclone V Device Datasheet