欢迎访问ic37.com |
会员登录 免费注册
发布采购

5CSEMA5U23I7N 参数 Datasheet PDF下载

5CSEMA5U23I7N图片预览
型号: 5CSEMA5U23I7N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 85000-Cell, CMOS, PBGA672, ROHS COMPLIANT, UBGA-672]
分类和应用: 可编程逻辑
文件页数/大小: 66 页 / 1360 K
品牌: INTEL [ INTEL ]
 浏览型号5CSEMA5U23I7N的Datasheet PDF文件第37页浏览型号5CSEMA5U23I7N的Datasheet PDF文件第38页浏览型号5CSEMA5U23I7N的Datasheet PDF文件第39页浏览型号5CSEMA5U23I7N的Datasheet PDF文件第40页浏览型号5CSEMA5U23I7N的Datasheet PDF文件第42页浏览型号5CSEMA5U23I7N的Datasheet PDF文件第43页浏览型号5CSEMA5U23I7N的Datasheet PDF文件第44页浏览型号5CSEMA5U23I7N的Datasheet PDF文件第45页  
Switching Characteristics  
Page 41  
Figure 11 shows the timing diagram for MDIO timing characteristics.  
Figure 11. MDIO Timing Diagram  
MDC  
Td  
MDIO_OUT  
MDIO_IN  
Th  
Tsu  
I2C Timing Characteristics  
Table 45 lists the I2C timing characteristics for Cyclone V devices.  
Table 45. I2C Timing Requirements for Cyclone V Devices  
Standard Mode  
Fast Mode  
Symbol  
Description  
Unit  
Min  
4.7  
4
Max  
10  
Min  
Max  
2.5  
Tclk  
Tclkhigh  
Tclklow  
Serial clock (SCL) clock period  
SCL high time  
0.6  
1.3  
µs  
µs  
µs  
SCL low time  
Setup time for serial data line (SDA) data to  
SCL  
Ts  
0.25  
0.1  
µs  
Th  
Hold time for SCL to SDA data  
0
4.7  
4
3.45  
0.2  
0
0.9  
0.2  
µs  
µs  
µs  
µs  
µs  
Td  
SCL to SDA output data delay  
Tsu_start  
Thd_start  
Tsu_stop  
Setup time for a repeated start condition  
Hold time for a repeated start condition  
Setup time for a stop condition  
0.6  
0.6  
0.6  
4
Figure 12 shows the timing diagram for I2C timing characteristics.  
Figure 12. I2C Timing Diagram  
I2C_SCL  
Td  
Ts  
Tsu_stop  
Tsu_start Thd_start  
Th  
Data In  
Data Out  
I2C_SDA  
July 2014 Altera Corporation  
Cyclone V Device Datasheet  
 复制成功!