Page 36
Switching Characteristics
Table 36 shows the examples of the maximum input jitter calculated with the
equation.
Table 36. Examples of Maximum Input Jitter
Input Reference Clock Period
Divide Value (NR)
Maximum Jitter
Unit
ns
40 ns
40 ns
40 ns
1
2
4
0.8
1.6
3.2
ns
ns
QSPI Timing Characteristics
Table 37 lists the queued serial peripheral interface (QSPI) timing characteristics for
Cyclone V devices.
Table 37. QSPI Timing Requirements for Cyclone V Devices
Symbol Description
Fclk CLK clock frequency
Tdutycycle
Tdssfrst
Min
—
Typ
—
Max
108
55
Unit
MHz
%
QSPI_CLK duty cycle
45
—
1/2 cycle of
QSPI_CLK
Output delay QSPI_SS valid before first clock edge
—
—
ns
Tdsslst
Tdio
Output delay QSPI_SS valid after last clock edge
IO Data output delay
–1
–1
—
—
1
1
ns
ns
Maximum data input delay from falling edge of
QSPI_CLK to data arrival at SoC. The delay field of
the qspiregs.rddatacap register can be
programmed to adjust the capture logic of the
incoming data.
Tdinmax
—
—
—
—
Figure 4 shows the timing diagram for QSPI timing characteristics. This timing
diagram illustrates clock polarity mode 0 and clock phase mode 0.
Figure 4. QSPI Timing Diagram
Tdsslst
QSPI_SS
Tdssfrst
QSPI_CLK
QSPI_DATA
Tdio
Tdinmax
Data Out
Data In
Cyclone V Device Datasheet
July 2014 Altera Corporation
INTEL [ INTEL ]
