Switching Characteristics
Page 35
HPS Specifications
This section provides HPS specifications and timing for Cyclone V devices.
For HPS reset, the minimum reset pulse widths for the HPS cold and warm reset
signals (HPS_nRST and HPS_nPOR) are six clock cycles of HPS_CLK1.
HPS Clock Performance
Table 34 lists the HPS clock performance for Cyclone V devices.
Table 34. HPS Clock Performance for Cyclone V Devices
Symbol/Description
mpu_base_clk (microprocessor unit clock)
main_base_clk (L3/L4 interconnect clock)
h2f_user0_clk
–C6
925
462
100
100
200
–C7, –I7
800
–A7
700
350
100
100
160
–C8
600
300
100
100
160
Unit
MHz
MHz
MHz
MHz
MHz
400
100
h2f_user1_clk
100
h2f_user2_clk
200
HPS PLL Specifications
HPS PLL VCO Frequency Range
Table 35 lists the HPS PLL VCO frequency range for Cyclone V devices. This
specification applies to all speed grade.
Table 35. HPS PLL VCO Frequency Range for Cyclone V Devices
Description
Minimum
Maximum
Unit
VCO range
320
1,850
MHz
HPS PLL Input Clock Range
The HPS PLL input clock range is 10 – 50 MHz. This clock range applies to both
HPS_CLK1 and HPS_CLK2 inputs.
For more information about the clock range for different values of clock select (CSEL),
refer to the Booting and Configuration chapter.
HPS PLL Input Jitter
Use the following equation to determine the maximum input jitter (peak-to-peak) the
HPS PLLs can tolerate. The divide value (NR) is the value programmed into the
denominator field of the VCO register for each PLL. The PLL input reference clock is
divided by this value. The range of the denominator is 1 to 64.
Maximum input jitter = Input clock period x Divide value (NR) x 0.02
July 2014 Altera Corporation
Cyclone V Device Datasheet
INTEL [ INTEL ]
