Page 34
Switching Characteristics
OCT Calibration Block Specifications
Table 32 lists the OCT calibration block specifications for Cyclone V devices.
Table 32. OCT Calibration Block Specifications for Cyclone V Devices
Symbol
Description
Min
Typ
Max
Unit
OCTUSRCLK
Clock required by OCT calibration blocks
—
—
20
MHz
Number of OCTUSRCLK clock cycles required for
RS OCT /RT OCT calibration
TOCTCAL
—
—
1000
32
—
—
Cycles
Cycles
Number of OCTUSRCLK clock cycles required for OCT code
to shift out
TOCTSHIFT
Time required between the dyn_term_ctrl and oe signal
transitions in a bidirectional I/O buffer to dynamically switch
between RS OCT and RT OCT
TRS_RT
—
2.5
—
ns
Figure 3 shows the timing diagram for the oe and dyn_term_ctrl signals.
Figure 3. Timing Diagram for the oe and dyn_term_ctrl Signals
Tristate
TX
Tristate
RX
RX
oe
dyn_term_ctrl
TRS_RT
TRS_RT
Duty Cycle Distortion (DCD) Specifications
Table 33 lists the worst-case DCD for Cyclone V devices. The output DCD cycle only
applies to the I/O buffer. It does not cover the system DCD.
Table 33. Worst-Case DCD on I/O Pins for Cyclone V Devices
–C6
–C7, –I7
–C8, –A7
Symbol
Unit
Min
Max
Min
45
Max
Min
45
Max
Output Duty Cycle
45
55
55
55
%
Cyclone V Device Datasheet
July 2014 Altera Corporation
INTEL [ INTEL ]
