Switching Characteristics
Page 33
DLL Range, DQS Logic Block and Memory Output Clock Jitter Specifications
Table 29 lists the DLL operating frequency range specifications for Cyclone V devices.
Table 29. DLL Operating Frequency Range Specifications for Cyclone V Devices
Unit
Parameter
–C6
–C7, –I7
–C8
DLL operating frequency range
167 – 400
167 – 400
167 – 333
MHz
Table 30 lists the DQS phase shift error for Cyclone V devices. This error specification
is the absolute maximum and minimum error.
Table 30. DQS Phase Shift Error Specification for DLL-Delayed Clock (tDQS_PSERR) for Cyclone V
Devices
Number of DQS Delay Buffer
–C6
–C7, –I7
–C8
Unit
2
40
80
80
ps
Table 31 lists the memory output clock jitter specifications for Cyclone V devices.
The memory output clock jitter measurements are for 200 consecutive clock cycles, as
specified in the JEDEC DDR2/DDR3 SDRAM standard.
The memory output clock jitter is applicable when an input jitter of 30 ps (p-p) is
applied with bit error rate (BER) 10–12, equivalent to 14 sigma.
Altera recommends using the UniPHY intellectual property (IP) with PHYCLK
connections for better jitter performance.
Table 31. Memory Output Clock Jitter Specification for Cyclone V Devices
–C6
–C7, –I7
–C8
Clock
Parameter
Symbol
Unit
Network
PHYCLK
PHYCLK
Min
Max
Min
Max
Min
Max
Clock period jitter
tJIT(per)
tJIT(cc)
–60
60
–70
—
70
–70
70
ps
ps
Cycle-to-cycle period
jitter
—
90
100
—
100
July 2014 Altera Corporation
Cyclone V Device Datasheet
INTEL [ INTEL ]
