Page 32
Switching Characteristics
Table 28. High-Speed I/O Specifications for Cyclone V Devices (1), (2), (3) (Part 2 of 2)
–C6
Min Typ
–C7, –I7
Max Min Typ
–C8, –A7
Unit
Symbol
Conditions
Max
Min Typ
Max
TX output clock duty
cycle for both True and
Emulated Differential I/O
Standards
tDUTY
45
—
—
50
—
—
55
45
—
—
50
—
—
55
45
—
—
50
—
—
55
%
ps
ps
True Differential I/O
Standards
200
250
200
250
200
300
Emulated Differential I/O
Standards with Three
External Output Resistor
Networks
tRISE & tFALL
Emulated Differential I/O
Standards with One
External Output Resistor
Network
—
—
—
—
—
—
300
200
300
—
—
—
—
—
—
300
250
300
—
—
—
—
—
—
300
250
300
ps
ps
ps
True Differential I/O
Standards
Emulated Differential I/O
Standards with Three
External Output Resistor
Networks
TCCS
Emulated Differential I/O
Standards with One
External Output Resistor
Network
—
—
300
—
—
300
—
—
300
ps
Receiver
SERDES factor
J = 4 to 10 (5)
(6)
(6)
(6)
—
875 (7)
(8)
—
840 (7)
(8)
—
640 (7) Mbps
f
HSDR (data rate)
SERDES factor J = 1 to 2,
Uses DDR Registers
(6)
(6)
(6)
(8)
—
—
—
—
—
—
Mbps
Sampling Window
—
—
350
—
350
—
350
ps
Notes to Table 28:
(1) When J = 1 or 2, bypass the serializer/deserializer (SERDES) block.
(2) For LVDS applications, you must use the PLLs in integer PLL mode.
(3) This is achieved by using the LVDS clock network.
(4) Clock Boost Factor (W) is the ratio between the input data rate and the input clock rate.
(5) The Fmax specification is based on the fast clock used for serial data. The interface Fmax is also dependent on the parallel clock domain which is
design dependent and requires timing analysis.
(6) The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional,
or local) that you use. The I/O differential buffer and input register do not have a minimum toggle rate.
(7) You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew
margin, transmitter channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin.
(8) The maximum ideal data rate is the SERDES factor (J) x PLL max output frequency (fout), provided you can close the design timing and the signal
integrity simulation is clean.You can estimate the achievable maximum data rate by performing link timing closure analysis. You must consider
the board skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.
Cyclone V Device Datasheet
July 2014 Altera Corporation
INTEL [ INTEL ]
