Switching Characteristics
Page 31
High-Speed I/O Specifications
Table 28 lists high-speed I/O timing for Cyclone V devices.
Table 28. High-Speed I/O Specifications for Cyclone V Devices (1), (2), (3) (Part 1 of 2)
–C6
Min Typ
–C7, –I7
Max Min Typ
–C8, –A7
Min Typ
Symbol
Conditions
Unit
Max
Max
f
HSCLK_in (input
clock frequency)
True Differential I/O
Standards
Clock boost factor W = 1
5
—
437.5
5
—
420
5
—
320
MHz
(4)
to 40
fHSCLK_in (input
clock frequency)
Single Ended I/O
Standards
Clock boost factor W = 1
5
5
—
—
320
420
5
5
—
—
320
370
5
5
—
—
275
320
MHz
MHz
(4)
to 40
fHSCLK_OUT (output
clock frequency)
—
Transmitter
SERDES factor
J = 4 to 10 (5)
(6)
(6)
(6)
(6)
(6)
(6)
—
—
840
—
—
740
—
—
640 Mbps
True Differential I/O
Standards - fHSDR
(data rate)
SERDES factor J = 1 to 2,
Uses DDR Registers
(8)
(8)
(8)
Mbps
Emulated
Differential I/O
Standards with
Three External
Output Resistor
Networks - fHSDR
(6)
(6)
(6)
SERDES factor J = 4 to 10
SERDES factor J = 4 to 10
—
—
640
170
—
—
640
170
—
—
550 Mbps
(7)
(data rate)
Emulated
Differential I/O
Standards with One
External Output
(6)
(6)
(6)
170 Mbps
Resistor Network -
(7)
fHSDR (data rate)
Total Jitter for Data Rate,
600 Mbps - 840 Mbps
—
—
—
—
350
—
—
—
—
380
—
—
—
—
500
ps
UI
tx Jitter - True
Differential I/O
Standards
Total Jitter for Data Rate,
< 600 Mbps
0.21
0.23
0.30
tx Jitter - Emulated
Differential I/O
Standards with
Three External
Output Resistor
Networks
Total Jitter for Data Rate
< 640 Mbps
—
—
—
—
500
—
—
—
—
500
—
—
—
—
500
ps
UI
tx Jitter - Emulated
Differential I/O
Standards with One
External Output
Resistor Network
Total Jitter for Data Rate
< 640 Mbps
0.15
0.15
0.15
July 2014 Altera Corporation
Cyclone V Device Datasheet
INTEL [ INTEL ]
