CV-51002
2015.12.04
72
FPP Configuration Timing when DCLK-to-DATA[] >1
Related Information
FPP Configuration Timing
Provides the FPP configuration timing waveforms.
FPP Configuration Timing when DCLK-to-DATA[] >1
Table 58: FPP Timing Parameters When DCLK-to-DATA[] Ratio is >1 for Cyclone V Devices
Use these timing parameters when you use the decompression and design security features.
Symbol
Parameter
nCONFIG low to CONF_DONE low
Minimum
Maximum
600
600
—
1506(80)
1506(81)
—
Unit
ns
ns
µs
µs
µs
µs
µs
ns
s
tCF2CD
tCF2ST0
tCFG
tSTATUS
tCF2ST1
—
nCONFIG low to nSTATUS low
nCONFIG low pulse width
—
2
nSTATUS low pulse width
268
nCONFIG high to nSTATUS high
nCONFIG high to first rising edge on DCLK
nSTATUS high to first rising edge of DCLK
DATA[] setup time before rising edge on DCLK
DATA[] hold time after rising edge on DCLK
DCLK high time
—
(82)
tCF2CK
1506
(82)
tST2CK
tDSU
tDH
2
5.5
—
—
(83)
N – 1/fDCLK
—
tCH
0.45 × 1/fMAX
—
s
tCL
DCLK low time
0.45 × 1/fMAX
—
s
tCLK
fMAX
tR
DCLK period
1/fMAX
—
—
s
DCLK frequency (FPP ×8/ ×16)
Input rise time
125
40
MHz
ns
—
(80)
(81)
(82)
(83)
This value can be obtained if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
This value can be obtained if you do not delay configuration by externally holding nSTATUS low.
If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification.
N is the DCLK-to-DATA[] ratio and fDCLK is the DCLK frequency of the system.
Cyclone V Device Datasheet
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