欢迎访问ic37.com |
会员登录 免费注册
发布采购

5CGTFD9E5F31C7N 参数 Datasheet PDF下载

5CGTFD9E5F31C7N图片预览
型号: 5CGTFD9E5F31C7N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 301000-Cell, CMOS, PBGA896, ROHS COMPLIANT, FBGA-896]
分类和应用: 可编程逻辑
文件页数/大小: 95 页 / 1359 K
品牌: INTEL [ INTEL ]
 浏览型号5CGTFD9E5F31C7N的Datasheet PDF文件第64页浏览型号5CGTFD9E5F31C7N的Datasheet PDF文件第65页浏览型号5CGTFD9E5F31C7N的Datasheet PDF文件第66页浏览型号5CGTFD9E5F31C7N的Datasheet PDF文件第67页浏览型号5CGTFD9E5F31C7N的Datasheet PDF文件第69页浏览型号5CGTFD9E5F31C7N的Datasheet PDF文件第70页浏览型号5CGTFD9E5F31C7N的Datasheet PDF文件第71页浏览型号5CGTFD9E5F31C7N的Datasheet PDF文件第72页  
CV-51002  
2015.12.04  
68  
CAN Interface  
CAN Interface  
The maximum controller area network (CAN) data rate is 1 Mbps.  
HPS JTAG Timing Specifications  
Table 53: HPS JTAG Timing Parameters and Values for Cyclone V Devices  
Symbol  
Description  
Min  
30  
14  
14  
2
Max  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tJCP  
tJCH  
tJCL  
TCK clock period  
TCK clock high time  
TCK clock low time  
tJPSU (TDI)  
tJPSU (TMS)  
tJPH  
TDI JTAG port setup time  
TMS JTAG port setup time  
JTAG port hold time  
JTAG port clock to output  
3
5
tJPCO  
12(72)  
14(72)  
14(72)  
tJPZX  
JTAG port high impedance to valid output  
JTAG port valid output to high impedance  
tJPXZ  
Configuration Specifications  
This section provides configuration specifications and timing for Cyclone V devices.  
(72)  
A 1-ns adder is required for each VCCIO _HPS voltage step down from 3.0 V. For example, tJPCO= 13 ns if VCCIO _HPS of the TDO I/O bank = 2.5 V, or  
14 ns if it equals 1.8 V.  
Cyclone V Device Datasheet  
Send Feedback  
Altera Corporation  
 复制成功!