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5CGTFD9E5F31C7N 参数 Datasheet PDF下载

5CGTFD9E5F31C7N图片预览
型号: 5CGTFD9E5F31C7N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 301000-Cell, CMOS, PBGA896, ROHS COMPLIANT, FBGA-896]
分类和应用: 可编程逻辑
文件页数/大小: 95 页 / 1359 K
品牌: INTEL [ INTEL ]
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CV-51002  
2015.12.04  
73  
AS Configuration Timing  
Symbol  
Parameter  
Minimum  
Maximum  
Unit  
ns  
tF  
tCD2UM  
tCD2CU  
Input fall time  
175  
40  
437  
CONF_DONE high to user mode(84)  
µs  
CONF_DONE high to CLKUSR enabled  
4 × maximum DCLK period  
tCD2UMC  
CONF_DONE high to user mode with CLKUSR option on  
tCD2CU + (Tinit × CLKUSR  
period)  
Tinit  
Number of clock cycles required for device initialization  
17,408  
Cycles  
Related Information  
FPP Configuration Timing  
Provides the FPP configuration timing waveforms.  
AS Configuration Timing  
Table 59: AS Timing Parameters for AS ×1 and ×4 Configurations in Cyclone V Devices  
The minimum and maximum numbers apply to both the internal oscillator and CLKUSR when either one is used as the clock source for device configura‐  
tion.  
The tCF2CD, tCF2ST0, tCFG, tSTATUS, and tCF2ST1 timing parameters are identical to the timing parameters for passive serial (PS) mode listed in PS Timing  
Parameters for Cyclone V Devices table. You can obtain the tCF2ST1 value if you do not delay configuration by externally holding nSTATUS low.  
Symbol  
Parameter  
Minimum  
Maximum  
Unit  
ns  
tCO  
tSU  
DCLK falling edge to the AS_DATA0/ASDO output  
Data setup time before the falling edge on DCLK  
Data hold time after the falling edge on DCLK  
CONF_DONE high to user mode  
2
1.5  
ns  
tDH  
0
175  
ns  
tCD2UM  
tCD2CU  
437  
µs  
CONF_DONE high to CLKUSR enabled  
4 × maximum DCLK period  
tCD2UMC  
CONF_DONE high to user mode with CLKUSR option on  
tCD2CU + (Tinit × CLKUSR  
period)  
(84)  
The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.  
Cyclone V Device Datasheet  
Send Feedback  
Altera Corporation  
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