CV-51002
2015.12.04
74
DCLK Frequency Specification in the AS Configuration Scheme
Symbol
Parameter
Minimum
Maximum
Unit
Tinit
Number of clock cycles required for device initialization
17,408
—
Cycles
Related Information
•
•
PS Configuration Timing on page 74
AS Configuration Timing
Provides the AS configuration timing waveform.
DCLK Frequency Specification in the AS Configuration Scheme
Table 60: DCLK Frequency Specification in the AS Configuration Scheme
This table lists the internal clock frequency specification for the AS configuration scheme. The DCLK frequency specification applies when you use the
internal oscillator as the configuration clock source. The AS multi-device configuration scheme does not support DCLK frequency of 100 MHz.
Parameter
Minimum
Typical
Maximum
Unit
5.3
7.9
12.5
MHz
MHz
MHz
MHz
10.6
15.7
31.4
62.9
25.0
DCLK frequency in AS configuration scheme
21.3
50.0
42.6
100.0
PS Configuration Timing
Table 61: PS Timing Parameters for Cyclone V Devices
Symbol
Parameter
nCONFIG low to CONF_DONE low
Minimum
Maximum
600
Unit
ns
tCF2CD
tCF2ST0
tCFG
—
—
2
nCONFIG low to nSTATUS low
nCONFIG low pulse width
nSTATUS low pulse width
600
ns
—
1506(85)
µs
tSTATUS
268
µs
(85)
You can obtain this value if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
Cyclone V Device Datasheet
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