CV-51002
2015.12.04
75
PS Configuration Timing
Symbol
Parameter
nCONFIG high to nSTATUS high
Minimum
Maximum
Unit
µs
µs
µs
ns
ns
s
tCF2ST1
—
1506(86)
—
(87)
tCF2CK
nCONFIG high to first rising edge on DCLK
nSTATUS high to first rising edge of DCLK
DATA[] setup time before rising edge on DCLK
DATA[] hold time after rising edge on DCLK
DCLK high time
1506
(87)
tST2CK
tDSU
tDH
2
—
5.5
—
0
—
tCH
0.45 × 1/fMAX
—
tCL
DCLK low time
0.45 × 1/fMAX
—
s
tCLK
fMAX
tCD2UM
tCD2CU
DCLK period
1/fMAX
—
s
DCLK frequency
—
175
125
437
—
MHz
µs
—
—
CONF_DONE high to user mode(88)
CONF_DONE high to CLKUSR enabled
CONF_DONE high to user mode with CLKUSR option on
4 × maximum DCLK period
tCD2UMC
tCD2CU + (Tinit × CLKUSR
—
period)
Tinit
Number of clock cycles required for device initialization
17,408
—
Cycles
Related Information
PS Configuration Timing
Provides the PS configuration timing waveform.
(86)
You can obtain this value if you do not delay configuration by externally holding nSTATUS low.
(87)
(88)
If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification.
The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
Cyclone V Device Datasheet
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