CV-51002
2015.12.04
70
FPP Configuration Timing
Symbol
Description
Min
Max
Unit
tJPXZ
JTAG port valid output to high impedance
—
14(75)
ns
FPP Configuration Timing
DCLK-to-DATA[] Ratio (r) for FPP Configuration
Fast passive parallel (FPP) configuration requires a different DCLK-to-DATA[] ratio when you turn on encryption or the compression feature.
Depending on the DCLK-to-DATA[] ratio, the host must send a DCLK frequency that is r times the DATA[] rate in byte per second (Bps) or word per
second (Wps). For example, in FPP ×16 where the r is 2, the DCLK frequency must be 2 times the DATA[] rate in Wps.
Cyclone V devices use additional clock cycles to decrypt and decompress the configuration data. If the DCLK-to-DATA[] ratio is greater than 1, at
the end of configuration, you can only stop the DCLK (DCLK-to-DATA[] ratio – 1) clock cycles after the last data is latched into the Cyclone V device.
Table 56: DCLK-to-DATA[] Ratio for Cyclone V Devices
Configuration Scheme
Encryption
Off
Compression
DCLK-to-DATA[] Ratio (r)
Off
Off
On
On
Off
Off
On
On
1
1
2
2
1
2
4
4
On
FPP (8-bit wide)
Off
On
Off
On
FPP (16-bit wide)
Off
On
FPP Configuration Timing when DCLK-to-DATA[] = 1
When you enable decompression or the design security feature, the DCLK-to-DATA[] ratio varies for FPP ×8 and FPP ×16. For the respective DCLK-
to-DATA[] ratio, refer to the DCLK-to-DATA[] Ratio for Cyclone V Devices table.
Cyclone V Device Datasheet
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