CV-51002
2015.12.04
71
FPP Configuration Timing when DCLK-to-DATA[] = 1
Table 57: FPP Timing Parameters When DCLK-to-DATA[] Ratio is 1 for Cyclone V Devices
Symbol
Parameter
nCONFIG low to CONF_DONE low
Minimum
Maximum
600
600
—
1506(76)
1506(77)
—
Unit
ns
ns
µs
µs
µs
µs
µs
ns
ns
s
tCF2CD
tCF2ST0
tCFG
tSTATUS
tCF2ST1
—
nCONFIG low to nSTATUS low
nCONFIG low pulse width
—
2
nSTATUS low pulse width
268
nCONFIG high to nSTATUS high
nCONFIG high to first rising edge on DCLK
nSTATUS high to first rising edge of DCLK
DATA[] setup time before rising edge on DCLK
DATA[] hold time after rising edge on DCLK
DCLK high time
—
(78)
tCF2CK
1506
(78)
tST2CK
tDSU
2
—
5.5
—
tDH
0
—
tCH
0.45 × 1/fMAX
—
tCL
DCLK low time
0.45 × 1/fMAX
—
s
tCLK
DCLK period
1/fMAX
—
s
fMAX
tCD2UM
tCD2CU
tCD2UMC
DCLK frequency (FPP ×8/ ×16)
CONF_DONE high to user mode(79)
CONF_DONE high to CLKUSR enabled
CONF_DONE high to user mode with CLKUSR option on
—
175
125
437
—
MHz
µs
—
—
4× maximum DCLK period
tCD2CU + (Tinit × CLKUSR
—
period)
Tinit
Number of clock cycles required for device initialization
17,408
—
Cycles
(76)
You can obtain this value if you do not delay configuration by extending the nCONFIG or the nSTATUS low pulse width.
You can obtain this value if you do not delay configuration by externally holding the nSTATUS low.
If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification.
The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
(77)
(78)
(79)
Cyclone V Device Datasheet
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